DSP Processors

Instructions & Programming 1

 LACC (Revisited)
• LACC – Load immediate or memory data in Accumulator
with left shift as specified by the instruction.
• ACC  2SHIFT × DATA

• The data may be specified using long immediate

addressing (2’s Complement Signed Constant), direct
addressing or indirect addressing.
• During the shift
– Lower order bits are filled with 0.

– Higher order bits are sign extended if SXM = 1.

• Let us consider following examples

Instructions & Programming 1 – Manish Tiwari 2

 LACC (Contd.)
e.g.
• LACC #8000H, 1 Load 8000H in ACC with 1-bit left shift
• CASE 1: SXM = 0

Before Execution After Execution

ACC 1001 2002H 0001 0000H
• CASE 2: SXM = 1

Before Execution After Execution

ACC 1001 2002H FFFF 0000H

Instructions & Programming 1 – Manish Tiwari 3

 LACC (Contd.)
Syntax:
Long Immediate: LACC #lk [,SHIFT] ; –32768 ≤ lk ≤ 32767
ACC  2SHIFT × lk
Direct: LACC dir [,SHIFT] ; 0 ≤ dir ≤ 127

Indirect: LACC {ind} [,SHIFT [,ARn]]

; 0  SHIFT  16 ;0n7
; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}
ACC  2SHIFT × (dma)
Operands in [ ] are optional.
Default SHIFT is 0.
Indirect Addressing always gives an option to change the current AR.

Instructions & Programming 1 – Manish Tiwari 4

 LACL
• Load a short constant or memory data into ACCL and
zero fill ACCH.
– ACCL  DATA

– ACCH  0

Syntax Short immediate: LACL #k ; 0≤ k ≤ 255

Direct: LACL dir ; 0 ≤ dir ≤
127
Indirect: LACL {ind} [,ARn] ;0≤n≤7
• During immediate, lower 8 bits of ACCL are loaded by
short constant k and upper 8 bits of ACCL are 0 filled.
Instructions & Programming 1 – Manish Tiwari 5
 LACL (Contd.)
• Ex. 1 LACL #10H
Before Instruction After
Instruction

ACC 1234 5678H 0000 0010H

• Ex. 2 LACL 01H (DP=06H)

DP (9-bits) dir (7-bits) Dma (16-bits)

0 0000 0110 000 0001 0301H

Before Instruction After

Instruction
Data Location
ABCDH ABCDH
0301H
ACC 1234 5678H 0000 ABCDH
Instructions & Programming 1 – Manish Tiwari 6
 SACL
• Store ACCL in data memory with left shift.
– ACCL × 2SHIFT2  (dma) ; dma – data memory address

Syntax

Direct: SACL dir [,SHIFT2] ; 0 ≤ dir ≤ 127

Indirect: SACL {ind} [,SHIFT2 [,ARn]]

;0≤n≤7

; 0  SHIFT2  7
• During the left shift, the lower order bits are 0 filled but
higher order bits are lost.
• ACC remains unaffected after the execution of SACL.
Instructions & Programming 1 – Manish Tiwari 7
 SACL (Contd.)
• Ex. 1 SACL *+, 0, AR7
– Store ACCL indirectly without left shift in memory, after
the memory operation increment current AR by 1 and then
change the current AR to AR7.

Before Instruction After

Instruction
ARP 6 7

AR6 020BH 020CH

ACC 1234 8421H 1234 8421H

Data Location
ABCDH 8421H
020BH
Instructions & Programming 1 – Manish Tiwari 8
 SACL (Contd.)
• Ex. 2 SACL 0BH,1 (DP=04)
DP (9-bits) dir (7-bits) Dma (16-bits)
0 0000 0100 000 1011 020BH

Before Instruction After

Instruction
ACC 1234 8421H 1234 8421H
Data Location
ABCDH 0842H
020BH
• ACCL × 2SHIFT2  8421H × 21 = 10842H  0842H is
stored. Recall that higher order bits are lost.

Instructions & Programming 1 – Manish Tiwari 9

 SACH
• Store ACCH in data memory with left shift.
– ACCH × 2SHIFT2  (dma) ; dma – data memory address

Syntax

Direct: SACH dir [,SHIFT2] ; 0 ≤ dir ≤ 127

Indirect: SACH {ind} [,SHIFT2 [,ARn]]

;0≤n≤7
; 0  SHIFT2  7
• During the left shift, first content of ACC (32-bits) is left
shifted and then higher order 16-bits are stored in
memory. ACC remains unaffected after the execution of
SACH.
Instructions & Programming 1 – Manish Tiwari 10
 SACH (Contd.)
• Ex. SACH *+, 1, AR2
– Store ACCH indirectly with 1-bit left shift in memory, after the
memory operation increment current AR by 1 and then change
the current AR to AR2.
Before Instruction After
Instruction
ARP 1 2

AR1 0300H 0301H

ACC 0420 8001H 0420 8001H

Data Location
FFFFH 0841H
0300H
– ACC × 2SHIFT2  04208001H × 21 = 0841 0002H  0841H is
stored.
Instructions & Programming 1 – Manish Tiwari 11
 LDP (Revisited)
• Load a 9-bit short constant either immediately or from
data memory into DP.
Syntax Short immediate: LDP #k ; 0≤ k ≤
511
Direct: LDP dir ; 0 ≤ dir ≤ 127
Indirect: LDP {ind} [,ARn] ;0≤n≤7
• During memory loads, lower 9 bits or 9 LSBs of memory
constant is loaded into DP.
– Recall that at each memory location in C5X, 16-bit word is stored.

• Ex. 1 LDP #04H After execution DP=04H.

Instructions & Programming 1 – Manish Tiwari 12

 LDP (Contd.)
• Ex. 2 LDP *+, AR2
– Load 9-bit constant indirectly in DP, after the memory
operation increment current AR by 1 and then change the
current AR to AR2.

Before Instruction After

Instruction
ARP 4 2

AR4 0300H 0301H

Data Location
2F80H 2F80H
0300H
DP 70H 180H
– 2F80H  0010 1111 1000 0000  1 1000 0000 = 180H  DP
Instructions & Programming 1 – Manish Tiwari 13
 Example Program 3
• Write a program to copy a data word from memory
location 020AH to 020BH.
DP dir
dma = 020AH = 0000 0010 0 | 000 1010
dma = 020BH = 0000 0010 0 | 000 1011
.entry
LDP #04 // Select memory page 04.
LACL 0AH // Read from 020Ah into ACCL.
SACL 0BH // Store at 020BH.
.end
Instructions & Programming 1 – Manish Tiwari 14
 LAMM Revisited
LAMM - Load Accumulator from Memory Mapped Register
Syntax Direct: LAMM dir ; 0 ≤ dir ≤
127
Indirect: LAMM {ind} [,ARn] ;0≤n≤7
ACCL  (Page 0 dma)
ACCH  0
Load is performed from Memory Page 0 Only and irrespective of
content of DP or Indirect Operand, the upper 9-bits of DAB are forced
to be 0 to read from Memory Page 0.
Ex. 1 – LAMM 0CH ; ACCL  TREG0 & ACCH  0
Ex. 2 – Let ARP = 01, AR1=100CH
LAMM * ; ACCL  TREG0 & ACCH  0
In indirect LAMM, only lower 7-bits of AR1 are placed on DAB and
upper 9-bits of DAB are forced to be 0.
Instructions & Programming 1 – Manish Tiwari 15
 SAMM Revisited
SAMM - Store Accumulator to Memory Mapped Register
Syntax Direct: SAMM dir ; 0 ≤ dir ≤
127
Indirect: SAMM {ind} [,ARn] ;0≤n≤7

ACCL  (Page 0 dma)

Store is performed in Memory Page 0 Only and irrespective of
content of DP or Indirect Operand, the upper 9-bits of DAB are
forced to be 0 to read from Memory Page 0.
Ex. 1 – SAMM 18H ; ACCL  INDX
Ex. 2 – SAMM INDX ; ACCL  INDX
Ex. 3 – Let ARP = 01, AR1=1018H
SAMM * ; ACCL  INDX
Instructions & Programming 1 – Manish Tiwari 16
 LMMR Revisited
LMMR- Load a data from data memory location into specified
Memory Mapped Register.
(Memory Mapped Register)  (dma)
Syntax Indirect: LMMR {ind}, #addr [,ARn] ;0≤n≤
7
Direct: LMMR dir, #addr ; 0 ≤ dir ≤ 127
;0  addr  FFFFH (16-bits)
Ex. 1 – LMMR DBMR, #2500H
Load DBMR from data memory address 2500H.
Ex. 2 – LMMR 0FH, #2500H
Load DBMR from data memory address 2500H. Address of DBMR is 0FH
in Page 0.

Instructions & Programming 1 – Manish Tiwari 17

 LMMR (Contd.)
• Ex. 3 LMMR *, #020AH, AR1
Before Instruction After
Instruction
ARP 6 1

AR6 030FH 030FH

Data Location
020AH F00FH F00FH
DBMR 01 F00FH
– Address in AR6 is 030F but for memory-mapped register
addressing upper 9-bits of DAB is forced to be 0. So,
effective address carried by DAB is 000FH which is
address of DBMR.
Instructions & Programming 1 – Manish Tiwari 18
 SMMR Revisited
LMMR- Store a data from specified Memory Mapped Register to
data memory location.
(Memory Mapped Register)  (dma)
Syntax Indirect: SMMR {ind}, #addr [,ARn] ;0≤n≤7
Direct: SMMR dir, #addr ; 0 ≤ dir ≤ 127
;0  addr  FFFFH (16-bits)
Ex. 1 – SMMR CBCR, #2500H; DP=06
Store CBCR at data memory address 2500H.
Ex. 2 – SMMR 1EH, #2500H ; DP=06
Store CBCR at data memory address 2500H. Address of CBCR is 1EH in
Page 0. Recall that upper 9-bits of DAB is forced to be 0 in memory-
mapped register addressing irrespective of DP.

Instructions & Programming 1 – Manish Tiwari 19

 LST
LST - Load status register from data memory
(STm)  (dma) ; m = 0 or 1 for ST0, ST1
(ARP)  (b15 – b13 of memory data)

Syntax Direct: LST #m, dir ; 0 ≤ dir ≤ 127

Indirect: LST #m, {ind} [,ARn] ;0≤n≤7
• Execution of LST #0
– does not affect INTM
– Does not affect ARB, even though new values are loaded in ARP.
• After the execution of LST #1 both ARP & ARB are same. It is
because execution of LST #1 loads ARB in ST1 but it also loads
ARP at the same time.
• Next ARP value specified in indirect addressing (i.e. specified
through [,ARn]) is ignored.

Instructions & Programming 1 – Manish Tiwari 20

 LST (Contd.)
ST0
ARP OV OVM 1 INTM DP
b15 – b13 b12 b11 b10 b9 b8 – b0

• Ex. 1 LST #0, 60H ; (DP=0)

Before Instruction After

Instruction
Data Location
FFFFH FFFFH
0060H
ST0 0400H FDFFH
ST1 C580H C580H
ARP=0, ARB=6, ARP=7, ARB=6,
INTM=0 INTM=0
– Execution of LST #0 didn’t affect INTM bit in ST0 and ARB in ST1.
Instructions & Programming 1 – Manish Tiwari 21
 LST (Contd.)
ST1
ARB CNF TC SXM C 11 HM 1 XF 11 PM
b15 – b12 b11 b10 b9 b8 – b6 b5 b4 b3 – b2 b1 – b0
b13 b7
• Ex. 2 LST #1, *+, AR1 ;
Before Instruction After Instruction
ARP 0 7
AR0 0060H 0061H
Data Location
0060H FFFFH FFFFH
ST0 0400H E400H
ST1 C580H FFFFH
ARP=0, ARB=6 ARP=7, ARB=7

– Note that LST ignores the specified next AR (i.e. AR1).

– LST is useful to restore status registers after the subroutine calls
and interrupts. 22
Instructions & Programming 1 – Manish Tiwari
 SST
SST - Store status register in data memory
(STm)  (dma) ; m = 0 or 1 for ST0, ST1
Syntax Direct: SST #m, dir ; 0 ≤ dir ≤ 127
Indirect: SST #m, {ind} [,ARn] ;0≤n≤7
• In the Direct Addressing Mode status registers always stored
in data memory Page 0 regardless of the status of DP.
– Helpful in interrupts, as original values of DP is stored in memory.
– Use addresses 60H to 7FH in direct addressing to store status
registers in Scratch Patch RAM i.e. in DARAM B2.
– Recall that addresses 00H to 5FH is reserved for memory mapped
registers in Page 0.
• Any data memory address can be used in case of Indirect
Addressing.

Instructions & Programming 1 – Manish Tiwari 23

 LAR
• Load specified AR either immediately or from memory.
– ARx  DATA ;0≤x≤7

Syntax Short immediate: LAR ARx, #k ; 0≤ k ≤ 255

Long immediate: LAR ARx, #lk ; 0≤ k ≤
65535
Direct: LAR ARx, dir ; 0 ≤ dir ≤
127
Indirect: LAR ARx, {ind} [,ARn] ; 0 ≤ n ≤ 7

• Note that long constant in LAR is unsigned. WHY?

Instructions & Programming 1 – Manish Tiwari 24
 LAR (Contd.)
• Ex. 1 LAR AR5, #0310H
Before Instruction After
Instruction

AR5 XXXX 0310H

• Ex. 2 LAR AR0, 10H (DP=06H)

DP (9-bits) dir (7-bits) Dma (16-bits)

0 0000 0110 001 0000 0310H

Before Instruction After

Instruction
Data Location
0310H 2050H 2050H

AR0 0310H 2050H

Instructions & Programming 1 – Manish Tiwari 25
 LAR (Contd.)
• Ex. 3 LAR AR6, *+

Before Instruction After

Instruction
ARP 6 6

AR6 020AH 2050H

Data Location
020AH 2050H 2050H
– In indirect LAR, if the AR to be loaded is same as current
AR (as in above example) then LAR ignores any
modification in AR. Therefore, in Example 3, AR6 is not
incremented after execution of LAR.

Instructions & Programming 1 – Manish Tiwari 26

 SAR
• Store the specified AR in data memory.
– ARx  (dma) ;0≤x≤7

Syntax
Direct: SAR ARx, dir ; 0 ≤ dir ≤ 127

Indirect: SAR ARx, {ind} [,ARn] ;0≤n≤

7
– In the indirect addressing, if the AR to be stored is same as
current AR and the content of AR is modified, then SAR
stores value before modification in AR.

Instructions & Programming 1 – Manish Tiwari 27

 SAR (Contd.)
• Ex. 1 SAR AR6, *+

Before Instruction After

Instruction
ARP 6 6

AR6 0301H 0302H

Data Location
0301H 0H 0301H
– SAR has stored the value of AR6 before modification in it.

Instructions & Programming 1 – Manish Tiwari 28

 MAR
• Modify the current AR and ARP and store and copy old
ARP in ARB.

Syntax Direct: MAR dir ; 0 ≤ dir ≤ 127

Indirect: MAR {ind} [,ARn] ;0≤n≤

7
– Direct MAR executes as NOP.

– In Indirect Addressing current AR and ARP is affected as

specified by the instruction.
AR  As specified by the instruction.
ARB  ARP
ARP  As specified by the instruction.
Instructions & Programming 1 – Manish Tiwari 29
 MAR (Contd.)
• Ex. 1 MAR *, AR1
After
Before Instruction
Instruction

ARP 4 1

ARB 7 4
• Ex. 2 MAR *+, AR5
After
Before Instruction
Instruction
AR1 34H 35H

ARP 1 5

ARB 7 1
Instructions & Programming 1 – Manish Tiwari 30
 Example Program 4
• Write a program to copy a data word from memory
location 020AH to 020BH using indirect addressing.
.entry LACL *+
LAR AR0, #020AH // AR0  Memory Location
020AH.
MAR *, AR0 // Set AR0 as current AR.
LACL * // Read from 020AH.
MAR *+ // Increment AR0 i.e. AR0  020BH.
SACL * // Store at 020BH.
.end
Instructions & Programming 1 – Manish Tiwari 31
 Alternate Program 4
• Write a program to copy a data word from memory
location 020AH to 020BH using indirect addressing.
.entry
LAR AR0, #020AH // AR0  Memory Location
020AH
MAR *, AR0 // Set AR0 as current AR.
LACL *+ // Read from 020AH and Increment
AR0.
SACL * // Store at 020BH.
.end
Instructions & Programming 1 – Manish Tiwari 32
 ADRK & SBRK
• ADRK #k ; 0≤ k ≤ 255
Add a small immediate or short constant to current
AR.
– Current AR  Current AR + k

• SBRK #k ; 0≤ k ≤ 255
Subtract a small immediate or short constant from
current AR.
– Current AR  Current AR - k

• ADRK and SBRK is performed in ARAU and hence,

are unsigned operations.
Instructions & Programming 1 – Manish Tiwari 33
 Alternate Program 4
• Write a program to copy a data word from memory
location 020AH to 020BH using indirect addressing.
.entry
LAR AR0, #020AH // AR0  Memory Location
020AH.
MAR *, AR0 // Set AR0 as current AR.
LACL * // Read from 020AH.
ADRK #1 // AR0  AR0+1 i.e. AR0  020BH.
SACL * // Store at 020BH.
.end
Instructions & Programming 1 – Manish Tiwari 34
 BRANCHING
• Jump or Branch unconditionally to specified
Program Memory Address (PMA).

Syntax B PMA [,{ind} [,ARn]] ; 0 ≤ PMA ≤

65535
– PC  PMA.

– Ex. 1 B 191H, *+, AR5 Instruction After

Before
Instruction
PC 202H 191H

ARP 1 5

AR1 100H 101H

Instructions & Programming 1 – Manish Tiwari 35
 DELAYED BRANCHING
• Delayed unconditional Branch to specified Program
Memory Address (PMA).

Syntax BD PMA [,{ind} [,ARn]] ; 0 ≤ PMA ≤

65535
PC  PMA.
– Same as unconditional branch, but jump is not performed
immediately.
– A 2-word instruction or Two 1-word instructions following
the Branch instruction are executed before the branching
takes place.
Instructions & Programming 1 – Manish Tiwari 36
 DELAYED BRANCHING (Contd.)
• Ex. 1
BD 191H ; Delayed branch to 191H
MAR *+, AR1
LDP #2 Branch Occurs
here.
ADD #02
– Branch to 191H is performed after the execution of LDP
instruction.
– ADD is not executed.

• The purpose of delayed branching is

– To avoid flushing the pipeline and causing extra cycles.
– Maximizing speed of code execution.
Instructions & Programming 1 – Manish Tiwari 37
 Indirect Branch - BACC
• BACC Jump or Branch to Program Memory
Address (PMA) specified by ACCL.
Syntax BACC
– PC  ACCL

• Ex. 1
– LACC #2050H; ACCL  2050h
– BACC ; Jump to program location 2050H.

• BACCD – Delayed BACC. Execution of BACC

delayed similar to BD.

Instructions & Programming 1 – Manish Tiwari 38

 BANZ
• BANZ Jump or Branch to specified Program Memory
Address (PMA) if current AR is not 0.

Syntax BANZ PMA [,{ind} [,ARn]] ; 0 ≤ PMA ≤ 65535

– IF: Current AR  0
PC  PMA
– ELSE: PC  PC+2
– Modify the current AR as specified in instruction. If no modification
is specified then the current AR is decrement by 1.

– During the execution, First AR is tested and if AR  0 branching

takes place i.e. PMA is transferred to PC then AR is modified.
– So, to make N-time looping, count in current AR should be N-1.

• BANZD – Delayed BANZ. BANZ delayed similar to BD.

Instructions & Programming 1 – Manish Tiwari 39
 BANZ (Contd.)
• Ex. 1 BANZ 191H
Before Instruction After Instruction

ARP 0 0

AR0 1 0

PC 2050H 191H

• Ex. 2 BANZ 191H, *+, AR5

Before Instruction After Instruction

ARP 0 5

AR0 1 2

PC 2050H 191H

Instructions & Programming 1 – Manish Tiwari 40

 BANZ (Contd.)
• Ex. 3 BANZ 191H
Before Instruction After Instruction

ARP 0 0

AR0 0 FFFFH

PC 2050H 2052H

• No branching takes place.

• BANZ first tests current AR for 0. Since AR0=0, PC is

simply incremented by 2 to execute next instruction in
sequence.
• Default modification to current AR is decrement by 1 so,
AR0 becomes FFFFH after the execution of BANZ.
Instructions & Programming 1 – Manish Tiwari 41
 Example Program 5
Four data words are stored at data memory
location 60H to 63H. Write a program to transfer
these data items to data locations 160H to 163H.

Address Data Address Data

0060H D0 0160H XX

0061H D1 0161H XX

0062H D2 0162H XX

0063H D3 0163H XX

Instructions & Programming 1 – Manish Tiwari 42

 Example Program 5
.entry
LAR AR2, #03H ; Set COUNTER (N-1).
LAR AR0, #60H ; Source Pointer, AR0  60H.
LAR AR1, #160H ; Target Pointer, AR1  160H.
BACK: MAR *, AR0 ; Source PTR (AR0) is current AR.
LACL *+ ; Read source data and increment
LACL *+,
source PTR. AR1
MAR *, AR1 ; Target PTR (AR1) is current AR.
SACL *+ ; Store data and increment target PTR.
SACL *+,
MAR *, AR2 ; COUNTER is current AR. AR2
BANZ BACK ; Go Back if Counter  0. Decrement
counter by 1.
BANZ BACK, AR0
.end
Instructions & Programming 1 – Manish Tiwari 43
 Alternate Program 5
.entry
LAR AR2, #03H ; Set COUNTER (N-1).
LAR AR0, #60H ; Source Pointer, AR0  60H.
LAR AR1, #160H ; Target Pointer, AR1  160H.
MAR *, AR0 ; Source PTR (AR0) is current AR.

BACK: LACL *+, AR1 ; Read source data increment

source PTR,
and Load Target PTR in ARP.

SACL *+, AR2 ; Store data, increment target PTR

and
and Load Counter in ARP.

BANZ BACK, AR0 ; Go Back if Counter  0. Decrement

counter by 1. and Load source PTR in ARP.
.end
Instructions & Programming 1 – Manish Tiwari 44
 Conditional Branch - BCND
• BCND Branch Conditionally to specified Program
Memory Address (PMA).
Syntax BCND PMA , Cond1 [,Cond2] [,Cond3] [,…….]
– IF: Conditions = TRUE
PC  PMA
– ELSE: PC  PC+2

• Ex. 1
– BCND 191H, LEQ, C
– Branch to program location 191H if ACC  0 and CY = 1.

• BCNDD – Delayed BCND. Execution of BCND delayed

similar to BD.
Instructions & Programming 1 – Manish Tiwari 45
 BCND (Contd.)
• Conditions used in BCND

Condition Symbol Condition Symbol

ACC = 0 EQ CY = 0 NC

ACC  0 NEQ CY = 1 C

ACC < 0 LT OV = 0 NOV

ACC  0 LEQ OV = 1 OV

ACC > 0 GT TC = 0 NTC

ACC  0 GEQ TC = 1 TC

Unconditional BIO Low BIO

UNC
ly

Instructions & Programming 1 – Manish Tiwari 46

 Example Program 6
Write a program to copy a standard C string to data
memory location 0250H from data memory location
04C0H.
.entry
LAR AR0, #04C0H ; Source Pointer, AR0  04C0H.
LAR AR1, #0250H ; Target Pointer, AR1  0250H.

BACK: MAR *, AR0 ; Source PTR (AR0) is current AR.

LACL *+, AR1 ; Read data, increment source PTR,
and Load Target PTR in ARP.
SACL *+, AR2 ; Store data, increment target PTR and
and Load Counter in ARP.
BCND BACK, NEQ ; Go Back if ACC  0.
.end

Instructions & Programming 1 – Manish Tiwari 47