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2 Sap

The document describes the architecture and operation of the SAP-1 (Simple As Possible) computer, detailing its components such as the program counter, memory unit, instruction register, and control unit. It outlines the basic instruction set, including memory-reference instructions and their corresponding opcodes, as well as the fetch and execution cycle. Additionally, it explains the function of various registers and the process of transferring data to and from the accumulator and output register.

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Minhaj Abedin Siam
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14 views37 pages

2 Sap

The document describes the architecture and operation of the SAP-1 (Simple As Possible) computer, detailing its components such as the program counter, memory unit, instruction register, and control unit. It outlines the basic instruction set, including memory-reference instructions and their corresponding opcodes, as well as the fetch and execution cycle. Additionally, it explains the function of various registers and the process of transferring data to and from the accumulator and output register.

Uploaded by

Minhaj Abedin Siam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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SAP-1

CSE 371
Basic Architecture
SAP (Simple As Possible) Computer
• A Bus organized computer
• All register output to the W bus are three-state, allowing orderly
transfer of data.
• All other register outputs are two-state.
Program Counter(pointer)

 A part of the Control Unit


 4-bit up counter, counts from 0000 to 1111.
 The program for the computer is stored at the beginning of the memory with the first instruction at
binary address 0000.
 The job of the program counter is to send to the memory the address of the next instruction to be
fetched and executed.
Operation of Program Counter
The program counter is reset to 0000 before each computer run
At the beginning it sends address 0000 to memory
Then the counter is incremented to 0001.
When the first instruction is fetched and executed, it sends address 0001.
And the process continues.
Hardware of Program Counter
RAM
Part of Memory Unit
16 byte static TTL RAM
Can be programmed by means of address and data switches
Receives address from MAR and places the stored content on the W bus.
Input and MAR

Contains address and data switch registers


Address and data switch registers are part of the input unit.
These registers allow programmers to send 4-bit addresses and 8-bit data bits
to RAM.
MAR (Memory Address Register) is a part of the memory unit.
During a computer run, the addresses of the program counter are latched
into it
These latched addresses are fed to RAM when a read operation is
performed.
Instruction Register
Part of the control unit.
To fetch an instruction from the memory the computer does a memory read
operation.
This places the contents of the addressed memory location on to W bus
At the same time the IR is set up for load on the next positive clock edge.
The contents of IR are divided into two nibbles.
The upper nibble is two states and goes to the controller/sequencer.
The lower nibble is three state output that is read onto the W bus when
needed
Controller/Sequencer
• Brain of the control unit.
• It has an instruction decoder, a ring counter, a clock, and a CON word
generator.
• Before each computer run, C/S sends a clear signal to reset the program
counter and IR.
• Sends clock signal to all buffer registers to synchronize the operation of the
computer
• The output of C/S is a 12 bit word known as Control Word (CON) contains
signals those controls the rest of the computer.
• These 12 bit signal constitutes what is called control bus.
Accumulator
Buffer register.
Two outputs
8 bit two-state output goes directly to adder/ subtracter,
8 bit three-state output goes to the W bus.
8 bit accumulator word continuously drives adder/ subtracter
The Same word appears on the W bus when is high.
Adder/Subtractor
2's complement adder/subtracter,
Performs
— addition when S u = 0.
— Subtraction when Su= 1.
Asynchronous — output changes as soon as the inputs change.
Output appears on the W bus when EU is high.
B Register
Buffer register.
Used in arithmetic operations.
Receives data from W bus.
Two state output drives the adder/subtracter supplying the number to be
added or subtracted from the content of the accumulator.
Output Register
At the end of a computer run, the accumulator contains the result.
Output register is used to transfer the result from the accumulator to the
outside world.
Also called Output Port since the processed data leave the computer through
this register.
In microcomputers the output port is connected to interface circuits that drive
peripheral devices like printers, cathode-ray tubes, teletypewriters, and so on.
Binary Display
• A row of eight LEDs.
• Shows the contents of the output register in binary form
Instruction Set and Programming
Instruction Set

• SAP-1 is a very primitive computer; hence, it can perform only Five basic instructions.
 LDA<memory_address> e.g. LDA AH
-Loads the accumulator with the contents of the memory address.
 ADD <memory_address> e.g, ADD AH
-Adds the contents of the memory address to the accumulator contents.
-sum replaces the original contents of the accumulator.
 SUB <memory address> e.g., SUB AH
-Subtracts the contents of the memory address from the accumulator contents.
-sum replaces the original contents of the accumulator.
 OUT ( Transfers the accumulator contents to the output)
 HLT ( No operation)
Memory-Reference Instructions
• LDA, ADD, and SUB are called memory-reference instructions
because they use data stored in the memory.
• OUT and HLT are not memory-reference instruction because they do
not involve data stored in the memory.
Mnemonics
• LDA, ADD, SUB, OUT, and HLT are the instruction set for
SAP-1.
• Abbreviated instructions like these are called mnemonics
(memory aids).
• Mnemonics are popular in computer work because they
remind of the operation that will take place when the
instruction is executed.
OPCODE
• The computer does not understand LDA, ADD, SUB, OUT, or HLT. Therefore, some kind of code is required
that the computer can interpret. The code that tells the computer which operation to perform is called an
operation code (opcode).
A Few Notes
 Assembly language involves working with mnemonics when
writing a program.
 The program written with mnemonics is called source program.
 Machine language involve working with strings of 0s and 1s.
 The program written with machine language is called object program
 In SAP-1 the operator translates the source program into an object
program
A Few Notes

• Note that the upper nibble (a nibble is a group of 4 consecutive bits) of


a SAP-l machine language instruction specifies the instruction whereas
the lower nibble provides the address required to complete the
instruction.
• Therefore the upper nibble is referred to as the instruction field and the
lower nibble is called the address field.
Fetch and Execution Cycle
CON Word for No Work
T states
T1

CON= 0101 1110 0011


=5E3 H
T2

CON= 1011 1110 0011


=BE3 H

T2:Increment State
T3

CON= 0010 0110 0011


= 26 3 H

T3: Memory State


T4<LDA>

CON= 0001 1010 0011


= 1A3 H
T5<LDA>

CON= 0010 1100 0011


= 2C3 H
T6<LDA>

CON= 0011 1110


0011
= 3E3 H

NOP
Self Study

• T4, T5, T6 for Other instructions

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