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Task Verilog

The document outlines various Verilog assignments and concepts, including the implementation of digital circuits such as subtractors, encoders, and flip-flops. It also explains procedural blocks, assign statements, operators, data types, arrays, and vectors in Verilog with pseudocode examples. Additionally, it includes tasks related to clock generation and duty cycle implementation.

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johnwickrj31
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6 views

Task Verilog

The document outlines various Verilog assignments and concepts, including the implementation of digital circuits such as subtractors, encoders, and flip-flops. It also explains procedural blocks, assign statements, operators, data types, arrays, and vectors in Verilog with pseudocode examples. Additionally, it includes tasks related to clock generation and duty cycle implementation.

Uploaded by

johnwickrj31
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Task_Verilog &

Assignments
By Aditi mam
1. single bit subtractor
2. 8*3 Encoder (Octal to Binary)
3. 4x1 Mux
4. 4x2 Priority encoder
5. 1x4 Demux
6. Excess3 to Binary code converter
7. 2 Bit Adder
8.Full adder using half adder
9. D Flip-Flop
10. S R Flip-Flop
11. J K Flip-Flop
12.T Flip-Flop
13.Write down verilog for this mention block
Test bench :
14. Read about procedural blocks and their functionality. Write a short note with pseudocode examples.

Procedural Blocks in Verilog:


Procedural blocks are used to describe sequential logic in Verilog. They are
classified into two main types:

1.always block
•Executes continuously, triggered by changes in sensitivity list.
•Commonly used for both combinational and sequential logic.

2.initial block
•Executes only once at the start of the simulation.
•Used for testbenches and initializing variables.
Example 1: Combinational Logic (Using always)
always @(*) begin
if (a && b)
out = 1;
else
out = 0;
end

Example 2: Sequential Logic (Flip-Flop)


always @(posedge clk) begin
if (reset) q <= 0;
else q <= d;
end
Example 3: Initial Block for Testbench
initial begin
clk = 0;
reset = 1;
#5 reset = 0;
end
15. Read about assign statement. Write a short note with pseudocode
examples.
• assign Statement in Verilog
The assign statement in Verilog is used for continuous assignments to describe
combinational logic
Key Points:
1.Purpose:
•Describes combinational circuits and logic without procedural blocks like
always.
•Automatically updates the output whenever inputs change.
2.Data Type:
•The output signal in an assign statement must be a wire type.
•Cannot assign values to reg using assign.
Example Pseudocode:

1.Half Adder:
assign sum = a ^ b; // XOR for sum
assign carry = a & b; // AND for carry

2.Comparator:
assign is_equal = (a == b); // Check equality
assign is_greater = (a > b); // Check greater than
16. Read about all the operators . Write working example codes for
each type of operator (logical, arithmetic, etc.).

1. Arithmetic Operators
These are used for performing basic mathematical operations like addition, subtraction,
multiplication, etc.

Example:

•+ Addition: Adds two operands. EX:assign sum = a + b;


•- Subtraction: Subtracts one operand from another. EX: assign diff = a - b;
•* Multiplication: Multiplies two operands. EX: assign prod = a * b;
•/ Division: Divides one operand by another. EX: assign div = a / b;
•% Modulus: Returns the remainder of division EX: assign mod = a % b
2. Logical Operators
Used to perform logical operations.

Example:
•&& Logical AND: Returns true if both operands are true. EX:assign result_and = a && b
•|| Logical OR: Returns true if at least one operand is true. EX:assign result_or = a || b;
•! Logical NOT: Returns true if the operand is false.EX: assign result_not = !a;

3. Relational Operators
These operators compare two operands and return a boolean result.
Example:
•== Equality: Returns true if operands are equal. Example: assign eq = (a == b);
•!= Inequality: Returns true if operands are not equal. Example: assign neq = (a != b);
•< Less than: Returns true if the left operand is smaller. Example: assign less = (a < b);
•> Greater than: Returns true if the left operand is larger. Example: assign greater = (a >
b);
3. Relational Operators

These operators compare two operands and return a boolean result.


Example:
•== Equality: Returns true if operands are equal. Example: assign eq = (a == b);
•!= Inequality: Returns true if operands are not equal. Example: assign neq = (a != b);
•< Less than: Returns true if the left operand is smaller. Example: assign less = (a < b);
•<= Less than or equal: Returns true if the left operand is smaller or equal. Example:
assign leq = (a <= b);
•> Greater than: Returns true if the left operand is larger. Example: assign greater =
(a > b);
•>= Greater than or equal: Returns true if the left operand is larger or equal.
Example: assign geq = (a >= b);
4. Bitwise Operators
Operate on individual bits of the operands.

Example:
•& Bitwise AND: Performs AND operation on each bit. Example: assign and_result = a & b;
•| Bitwise OR: Performs OR operation on each bit. Example: assign or_result = a | b;
•^ Bitwise XOR: Performs XOR operation on each bit. Example: assign xor_result = a ^ b;
•~ Bitwise NOT: Inverts all bits. Example: assign not_result = ~a;

5. Shift Operators
Shift the bits of the operand left or right.

Example:
•<< Left shift: Shifts bits to the left, filling with 0. Example: assign shifted_left = a << 2;
•>> Right shift: Shifts bits to the right. Example: assign shifted_right = a >> 2;
17.Read about all the data types. Write example codes for showing
use and format specifiers for displaying each data types.
18.Read about arrays and vectors in verilog. Write short note woth
examples of how to instantiate them.
1. Vectors
Vectors represent a group of related signals packed into a single variable. They are
commonly used to represent multi-bit signals like buses.

Syntax and Example:


• 2. Arrays
• Arrays are collections of multiple variables of the same type, indexed
for easy access.
• Syntax and Example:
19.Create a 10 element array of vector of sizr of 8 bits. Initialize each
vector value to 8'hac. Displaying entire array.
20.How to implement duty cycle cycle in clock generation
21.Try Different Time scale and try to generate same frequency

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