CS 5513: Computer Architecture

Lecture 1: Introduction

Daniel A. Jiménez
The University of Texas at San Antonio
http://www.cs.utsa.edu/~dj
http://www.cs.utsa.edu/~dj/cs5513
Outline

• Computer Science at a Crossroads

• Computer Architecture v. Instruction Set Arch.

• What Computer Architecture brings to table

 Crossroads: Conventional Wisdom in Comp. Arch
• Old Conventional Wisdom: Power is free, Transistors expensive
• New Conventional Wisdom: “Power wall” Power expensive, Xtors free
(Can put more on chip than can afford to turn on)
• Old CW: Sufficiently increasing Instruction Level Parallelism via
compilers, innovation (Out-of-order, speculation, VLIW, …)
• New CW: “ILP wall” law of diminishing returns on more HW for ILP
• Old CW: Multiplies are slow, Memory access is fast
• New CW: “Memory wall” Memory slow, multiplies fast
(200 clock cycles to DRAM memory, 4 clocks for multiply)
• Old CW: Uniprocessor performance 2X / 1.5 yrs
• New CW: Power Wall + ILP Wall + Memory Wall = Brick Wall
– Uniprocessor performance now 2X / 5(?) yrs
 Sea change in chip design: multiple “cores”
(2X processors per chip / ~ 2 years)
» More simpler processors are more power efficient
 Crossroads: Uniprocessor Performance
10000
From Hennessy and Patterson, Computer
Architecture: A Quantitative Approach, 4th
edition, October, 2006 ??%/year
Performance (vs. VAX-11/780)

1000

52%/year

100

10
25%/year

1
1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006
• VAX : 25%/year 1978 to 1986
• RISC + x86: 52%/year 1986 to 2002
• RISC + x86: 18%/year 2002 to 2008
 Sea Change in Chip Design
• Intel 4004 (1971): 4-bit processor,
2312 transistors, 0.4 MHz,
10 micron PMOS, 11 mm2 chip

• RISC II (1983): 32-bit, 5 stage

pipeline, 40,760 transistors, 3 MHz,
3 micron NMOS, 60 mm2 chip

• 125 mm2 chip, 0.065 micron CMOS

= 2312 RISC II+FPU+Icache+Dcache
– RISC II shrinks to ~ 0.02 mm2 at 65 nm
– Caches via DRAM or 1 transistor SRAM?

• Processor is the new transistor?

 Problems with Sea Change

• Algorithms, Programming Languages, Compilers,

Operating Systems, Architectures, Libraries, … not
ready to supply Thread Level Parallelism or Data
Level Parallelism for 1000 CPUs / chip,
• Architectures not ready for 1000 CPUs / chip
• Unlike Instruction Level Parallelism, cannot be solved by just by
computer architects and compiler writers alone, but also cannot
be solved without participation of computer architects
Instruction Set Architecture: Critical
Interface
software

instruction set

hardware

• Properties of a good abstraction

– Lasts through many generations (portability)
– Used in many different ways (generality)
– Provides convenient functionality to higher levels
– Permits an efficient implementation at lower levels
 Example:
r0 MIPS
0 Programmable storage Data types ?
r1
° 2^32 x bytes Format ?
° 31 x 32-bit GPRs (R0=0)
° Addressing Modes?
r31 32 x 32-bit FP regs (paired DP)
PC HI, LO, PC
lo
hi
Arithmetic logical
Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU,
AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI
SLL, SRL, SRA, SLLV, SRLV, SRAV
Memory Access
LB, LBU, LH, LHU, LW, LWL,LWR
SB, SH, SW, SWL, SWR
Control 32-bit instructions on word boundary
J, JAL, JR, JALR
BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL
 Instruction Set
Architecture
“... the attributes of a [computing] system as seen by
the programmer, i.e. the conceptual structure and
functional behavior, as distinct from the organization
of the data flows and controls the logic design, and
the physical implementation.”
– Amdahl, Blaauw, and Brooks, 1964
SOFTWARE
-- Organization of Programmable
Storage
-- Data Types & Data Structures:
Encodings & Representations
-- Instruction Formats
-- Instruction (or Operation Code) Set
-- Modes of Addressing and Accessing Data Items and Instructions
-- Exceptional Conditions
ISA vs. Computer Architecture
• Old definition of computer architecture
= instruction set design
– Other aspects of computer design called implementation
– Insinuates implementation is uninteresting or less challenging
• Our view is computer architecture >> ISA
• Architect’s job much more than instruction set
design; technical hurdles today more challenging
than those in instruction set design
• Since instruction set design not where action is,
some conclude computer architecture (using old
definition) is not where action is
– We disagree on conclusion
– Agree that ISA not where action is
 Comp. Arch. is an Integrated Approach

• What really matters is the functioning of the complete

system
– hardware, runtime system, compiler, operating system, and
application

• Computer architecture is not just about transistors,

individual instructions, or particular implementations
– E.g., Original RISC projects replaced complex instructions with a
compiler + simple instructions
 Computer Architecture is
Design and Analysis
Architecture is an iterative process:
• Searching the space of possible designs
Design
• At all levels of computer systems
Analysis

Creativity
Cost /
Performance
Analysis

Good Ideas
Mediocre Ideas
Bad Ideas
 CS 5513 Administrivia
Instructor: Prof. Daniel A. Jiménez
Office: SB 4.01.58
Office Hours: By appointment
T. A: Xinran Yu
Office: Office Hours in Main Lab
Office Hours: Monday, 3:00pm to 4:30pm
Class: Tuesday/Thursday 5:30pm to 6:45pm, HSS 3.04.28
Text: Hennessy and Patterson, Computer Architecture: A
Quantitative Approach, 4th Edition
Web page: http://www.cs.utsa.edu/~dj/cs5513

See web page for reading and homework assignments

 CS 5513 Course Focus
Understanding the design techniques, machine structures,
technology factors, evaluation methods that will
determine the form of computers in 21st Century

Technology Parallelism Programming

Languages
Applications Interface Design
Computer Architecture: (ISA)
• Organization
• Hardware/Software
Boundary Compilers

Operating Measurement &

Systems Evaluation History
 Research Paper Reading
• As graduate students, you are now researchers
• Most information of importance to you will be in
research papers
• Ability to rapidly scan and understand research papers
is key to your success

• So: you will read a few papers in this course

– The structure of this reading is to be decided
• Papers will be on web page
Related Courses

Prerequisites for CS 5513

CS 3733 – Operating Systems (requires CS 3843)
CS 4753/CS 3853 – Computer Architecture
both of these prerequire:
CS 3843 – Computer Organization
CS 3823 – Programming Languages
knowledge of C/C++/Java and assembly language

Classes with CS 5513 as a prerequisite

CS 6513 – Advanced Architecture
CS 6553 – Performance Evaluation
CS 6643 – Parallel Processing
CS 6653 – Parallel Algorithms
 Coping with CS 5513

• Students without proper prerequisites will have a

difficult time in this class. It is often difficult for
the graduate studies committee to determine
whether a class from another university is
equivalent to one of our prerequisites.
• We will have an “entrance quiz” to help you
determine whether you would like to enroll in a
different class.
• Will spend a few lectures reviewing material that is
also covered in an undergrad computer
architecture class.
Grading
• 15% Homeworks
• 25% Midterm Exam(s)
• 25% Second Exam
• 25% Project
– Transition from undergrad to grad student
– We want you to succeed, but you need to show initiative
– pick topic (more on this later)
– meet with faculty to gauge progress
– written report like conference paper
– work in groups
– Opportunity to do “research in the small” to help make transition
from good student to research colleague
• 10% Class Participation
– Contribute to the class discussion
Outline

• Computer Science at a Crossroads

• Computer Architecture v. Instruction Set Arch.

• What Computer Architecture brings to table

What Computer Architecture brings to Table
• Other fields often borrow ideas from architecture
• Quantitative Principles of Design
1. Take Advantage of Parallelism
2. Principle of Locality
3. Focus on the Common Case
4. Amdahl’s Law
5. The Processor Performance Equation
• Careful, quantitative comparisons
– Define, quantity, and summarize relative performance
– Define and quantity relative cost
– Define and quantity dependability
– Define and quantity power
• Culture of anticipating and exploiting advances in
technology
• Culture of well-defined interfaces that are carefully
implemented and thoroughly checked
1) Taking Advantage of Parallelism
• Increasing throughput of server computer via
multiple processors or multiple disks
• Detailed HW design
– Carry lookahead adders uses parallelism to speed up computing
sums from linear to logarithmic in number of bits per operand
– Multiple memory banks searched in parallel in set-associative
caches
• Pipelining: overlap instruction execution to reduce
the total time to complete an instruction sequence.
– Not every instruction depends on immediate predecessor 
executing instructions completely/partially in parallel possible
– Classic 5-stage pipeline:
1) Instruction Fetch (Ifetch),
2) Register Read (Reg),
3) Execute (ALU),
4) Data Memory Access (Dmem),
5) Register Write (Reg)
Pipelined Instruction Execution
Time (clock cycles)

Cycle 1Cycle 2 Cycle 3 Cycle 4Cycle 5 Cycle 6Cycle 7

I

ALU
Reg
n Ifetch Reg DMem

s
t
r.

ALU
Ifetch Reg DMem Reg

O
r

ALU
Ifetch Reg DMem Reg

d
e
r

ALU
Ifetch Reg DMem Reg
Limits to pipelining

• Hazards prevent next instruction from executing

during its designated clock cycle
– Structural hazards: attempt to use the same hardware to do
two different things at once
– Data hazards: Instruction depends on result of prior
instruction still in the pipeline
– Control hazards: Caused by delay between the fetching of
instructions and decisions about changes in control flow
(branches and jumps). Time (clock cycles)

ALU
I Ifetch Reg DMem Reg
n
s

ALU
Ifetch Reg DMem Reg
t
r.

ALU
Ifetch Reg DMem Reg

ALU
r Ifetch Reg DMem Reg
d
e
r
 2) The Principle of Locality
• The Principle of Locality:
– Program access a relatively small portion of the address space at any instant of time.
• Two Different Types of Locality:
– Temporal Locality (Locality in Time): If an item is referenced, it will tend to be
referenced again soon (e.g., loops, reuse)
– Spatial Locality (Locality in Space): If an item is referenced, items whose addresses
are close by tend to be referenced soon
(e.g., straight-line code, array access)
• Last 30 years, HW relied on locality for memory perf.

P $ MEM
 Capacity
Levels of the Memory Hierarchy
Access Time Staging
Cost Xfer Unit
CPU Registers
Registers Upper Level
100s Bytes
300 – 500 ps (0.3-0.5 ns) prog./compiler
Instr. Operands 1-8 bytes faster
L1 and L2 Cache L1 Cache
10s-100s K Bytes cache cntl
~1 ns - ~10 ns Blocks 32-64 bytes
$1000s/ GByte
L2 Cache
cache cntl
Main Memory Blocks 64-128 bytes
G Bytes
80ns- 200ns Memory
~ $100/ GByte
OS
Pages 4K-8K bytes
Disk
10s T Bytes, 10 ms
(10,000,000 ns)
Disk
~ $1 / GByte user/operator
Files Mbytes
Larger
Tape
infinite Tape Lower Level
sec-min
~$1 / GByte
3) Focus on the Common Case
• Common sense guides computer design
– Since its engineering, common sense is valuable
• In making a design trade-off, favor the frequent
case over the infrequent case
– E.g., Instruction fetch and decode unit used more frequently
than multiplier, so optimize it 1st
– E.g., If database server has 50 disks / processor, storage
dependability dominates system dependability, so optimize it 1st
• Frequent case is often simpler and can be done
faster than the infrequent case
– E.g., overflow is rare when adding 2 numbers, so improve
performance by optimizing more common case of no overflow
– May slow down overflow, but overall performance improved by
optimizing for the normal case
• What is frequent case and how much performance
improved by making case faster => Amdahl’s Law
 4) Amdahl’s Law
 Fraction 
ExTime
new  ExTime 
old  1  Fraction 
enhanced  enhanced

 Speedup 
enhanced

ExTime
old 1
Speedup
overall 
ExTime Fraction
new 1  Fraction 
enhanced
enhanced
Speedup
enhanced

Best you could ever hope to do:

1
Speedup
maximum
1 - Fractionenhanced
Amdahl’s Law example
• New CPU 10X faster
• I/O bound server, so 60% time waiting for I/O

1
Speedup overall 
Fraction enhanced
1  Fraction enhanced 
Speedup enhanced
1 1
  1.56
0.4 0.64
1  0.4
10
• Apparently, its human nature to be attracted by 10X
faster, vs. keeping in perspective its just 1.6X faster
 CPI
5) Processor performance equation
inst count Cycle time
CPU
CPUtime
time == Seconds
Seconds == Instructions
Instructions xx Cycles
Cycles xx
Seconds
Seconds
Program
Program Program
Program Instruction
Instruction Cycle
Cycle
Inst Count CPI Clock Rate
Program X

Compiler X (X)

Inst. Set. X X

Organization X X

Technology X
What’s a Clock Cycle?

Latch combinational
or logic
register

• Old days: 10 levels of gates

• Today: determined by numerous time-of-flight
issues + gate delays
– clock propagation, wire lengths, drivers
And in conclusion …
• Computer Architecture >> instruction sets
• Computer Architecture skill sets are different
– 5 Quantitative principles of design
– Quantitative approach to design
– Solid interfaces that really work
– Technology tracking and anticipation
• CS 5513 to learn new skills, transition to research
• Computer Science at the crossroads from
sequential to parallel computing
– Salvation requires innovation in many fields, including
computer architecture
• Read Chapter 1, then Appendices A & B.