A.R.M.

ADVANCED RISC MACHINE

“STEPS OF ARM”
 ADDRESSING SPACE AND MODES IN
ARM
◆ Larger address space
- use 16-bit, 32-bit or wider address bus.

◆ Addition addressing modes

- addressing modes are the different ways
that the operand address may be
specified.

◆ Subroutine call mechanism

- this allows writing modular programs.
Additional internal registers
- this reduces the need for accessing external
memory

Other system support mechanism such

as interrupts, direct memory access, cache
memory, memory management

Allows coprocessors to be added (such

as floating point)
 Instruction formats
4-address instruction format (not used in
ARM)
3-address instruction format (used by ARM
processor)
2-address instruction format (used by the
Thumb instruction set of ARM)
1-address instruction format (used in 8-
bit microcontrollers such as MC6811)
 How to make CPU faster?
◆ Wide instruction code and as few words (bytes) as
possible
❖ 8 bit / 16 bit / 32 bit / 64 bit processors
◆ Each instruction uses as few clock cycles as
possible
◆ Keep as much data inside CPU as possible (many
internal registers)
◆ Make each clock cycle as short as possible (high
clock rate)
 Design approaches
◆ Complex Instruction Set Computers (CISC)
❖ simple compiler
❖ powerful instruction set, variable format,
multi-word
❖ multi-cycle execution

◆ Reduced Instruction Set Computers (RISC)

❖ high clock rate, low development cost (?)
❖ easy to move to new technology
❖ simple instructions, fixed format, complex
optimizing compiler
◆ Fast local storage
❖ Register file, on-chip memory,
RAM
◆ Direct hardware implementation
❖ reconfigurable computing - no
fetch/decode
 ARM’s Market study
intellectual property (IP) provider of
high- performance, low-cost, power-efficient RISC
processors, peripherals, and system-chip (SoC)
designs.

ARM licenses IP to leading international electronics

companies ranging from semiconductor providers to
original equipment manufacturers (OEM).
 ARM
sells software and development systems
and provides consulting, support,
maintenance and training services, to
accelerate the acceptance of its
architecture and products.
 Introduction
ARM offers the industry’s broadest range of 16/32-
bit embedded RISC cores that are grouped into a
range of families:
– ARM 7 {(ARM7TDMI, ARM7TDMI-S), (ARM720T, ARM7EJ-S)}
– ARM 9 {ARM9TDMI, (ARM920T, ARM940T)}
– ARM 9E {ARM926EJ-S, ARM946E-S, ARM966E-S}
– ARM 10 {ARM1020E, ARM1022E}
– ARM 11 {(ARM1136J-S, ARM1136JF-S), (ARM1156T2-S, ARM1156T2F-S)
, (ARM1176JZ-S, ARM1156JZF-S)}
– SecureCore {SC100, SC110, SC200, SC210}

Each product family consists of high-performance,

energy- efficient designs built to handle the
performance demands of today’s increasingly
complex electronics applications.
ARM7:
Current Core Families
– IP Cores
– Cache with MPU or MMU (Memory protection/Management Unit)
– Real-time debug (RTD) and real-time trace (RTT)
ARM9/ARM9E-S:
– IP Cores
– Cache with MPU or MMU
– DSP
– RTD and RTT
ARM10E:
– Vector floating point (VFP) features
– RTD and RTT
– All cores incorporate I- and D-cache
StrongARM®:
– Cache with MMU
XScale
 First look at ARM
❖ Load-Store architecture
❖ Fixed-length (32-bit) instructions
❖ 3-address instruction formats (2 source operand
registers, 1 result operand register)
❖ Conditional execution of ALL instructions
❖ A single-cycle n-bit shift with ALU operation
❖ Coprocessor instruction interfacing
❖ Thumb architecture (16-bit compressed
instruction set)
 Programmers model
◆R0 to R14 are general purpose registers
(32-bits)
❖ Used by programmer for (almost)
any purpose without restriction
◆R15 is the Program Counter (PC)
◆The remaining shaped ones are system
mode registers – used during interrupts,
exceptions or system programming (to be
considered in later lectures)
◆Current Program Status Register (CPSR)
contains conditional flags
 Key features of ARM instruction set
 Load-store architecture
 3-address data processing instructions
 Conditional execution of EVERY instruction
 Perform a general shift operation and a general
ALU operation in a single instruction executed in
one cycle
 Can extend instruction set through the
coprocessor instruction set, including adding new
registers and data types
 Combines the best of RISC and the best of CISC
 ARM system
 Handles all input/output peripherals (such as
printer, disk and network) as memory-mapped
devices
 Two types of interrupt support - normal interrupt
and fast interrupt (considered in later lecture)
 Direct memory access (DMA) hardware support
for high-bandwidth data transfer (also later)
 Peripherals
❖ Parallel Peripheral Interface 82C55
❖ Counter/Timer Interface 82C54
❖ Universal Asynchronous Rx/Tx (UART) 16C450
❖ Pulse Width Modulator
❖ Interrupt Controller (eg 8259, 82c59)
 ARM development tools
 ARM C compiler - ANSI standard, fast, integrated
 ARM Assembler - translate assembly instructions to ARM
instructions
 Linker
 Takes one or more object files (from C compiler or ARM
assembler) and combines them into one executable
program
 Resolve symbolic references (i.e. names of variables or
routines are turned into actual memory addresses)
 ARM symbolic debugger - full control on execution and
viewing of registers
 ARMulator - emulate the ARM processes with a system
❖ Instruction-accurate modelling
❖ Cycle-accurate modelling
❖ Timing-accurate modelling
 Window User's interface
Evolution of
the
ARM
Architecture

ARM1136J(F)-S
ARM7 TDMI
 The ARM7TDMI™ Core
Most widely used
32-bit embedded processor
Ideal for the following applications:
– Personal audio
– Cell phones
– Modems
– Wireless handsets
– Pagers
– Inkjet printers
– Digital cameras
– PDA
 ARM7 TDMI - Features
32-bit RISC Architecture
Two Instruction Sets:
– ARM High-performance 32-bit Instruction Set
– Thumb High-code-density 16-bit Instruction Set
Von Neumann Load/Store Architecture:
– Single 32-bit Bus for Instructions and Data
3-Stage Pipeline Architecture:
– Fetch, Decode and Execute Stage
 ARM features Contd
Very Low Power Consumption: Industry-
leader in MIPS/Watt
4G Bytes Linear Address Space
8-, 16-, and 32-bit Data Types
Single Cycle 32x8 Hardware Multiplier
On-chip JTAG Debug and In Circuit
Emulation
Extensive Range of Third-party Application
Development Tools
ARM7TDMI Block Diagram
 The 3-Stage ARM Pipeline
fetch
– the instruction is fetched from memory
decode
– decoding of instruction and generation of control
signals
execute
– Register(s) read from register bank to perform
shift & ALU operations and the result written back
to register bank
Pipeline
 ARM Operating Modes
protected or exception modes which have
associated interrupt sources and their own
register sets.
– User (usr): Normal ARM program execution state
– Class 1: Exception caused mode change
Abort mode (abt): Entered after an illegal
memory accesses (mem fault) as a result of
fetching instructions or accessing data
Undefined (und): Entered when an undefined
or illegal instruction is executed
– Class 2: Interrupt caused mode change
FIQ (fiq): Processing Fast Interrupts
(Supports data transfer)
IRQ (irq): Processing Standard interrupts

– Class 3: Software Interrupt

Supervisor (svc): Protected mode for the
operating system, sw interrupts(SWI)
System (sys): A privileged user mode for
the operating system, entered when dealing
with nested interrupts
 Mode Change
– Exception: Switch to Abort or Undefined
mode
– Interrupts: Switch to FIQ/IRQ mode
– System Calls: Switch to Supervisor mode
 Architecture Basics

37 total registers (31 GP & 6 Status

Registers) for seven processor modes:
– 18 visible 32-bit registers in privileged modes (17
in user mode)
r0-r13 = general purpose registers (r13 = stack pointer
(SP))
r14 = link register (LR)
r15 = program counter (PC)
CPSR = current program status register
SPSR = saved program status register (only accessible
in privileged modes)
Fixed Mapping Based on Processor
Mode
– Mapping 37 registers into 17 registers
– Virtually every operating mode has its
private:
Link Register-R14
Stack Pointer-R13
 User Level
ARM’s visible – 15 GPRs, PC, CPSR
– Remaining registers
Register are used for system-level
programming & for handling
exceptions
Curent program status register and
flags
Exception And Interrupt Modes
User: This mode is used to run the application
code. Once in user mode the CPSR cannot be
written to and modes can only be changed when
an exception is generated.
FIQ: (Fast Interrupt reQuest) This supports high
speed interrupt handling. Generally it is used for
a single critical interrupt source in a system
IRQ: (Interrupt ReQuest) This supports all other
interrupt sources in a system
 Modes contd
Supervisor: A “protected” mode for
running system level code to access
hardware or run OS calls. The ARM 7
enters this mode after reset.
Abort: If an instruction or data is fetched
from an invalid memory region, an abort
exception will be generated
Undefined Instruction: If a FETCHED
opcode is not an ARM instruction, an
undefined instruction exception will be
generated
ARM7 Vector table
 What is TDMI?
Thumb
– 16-bit extensions to the 32-bit ARM instruction
set
Debug
– Additional core signals for debug use
Multiplier
– 32x8 bit multiplier (enhanced beyond 32x2 bit
in ARMv3…booth’s algorithm)
EmbeddedICE Logic
– logic/registers to control debug facilities

Thumb & ARM are referred to here as ‘states of the processor’

 Thumb Features
A subset of the 32-bit ARM instructions that can
be compressed into 16-bits:
– Selection based on the C compiler’s needs.
– Processor core executes both 16- and 32-bit
instructions segments.
Thumb programs typically are:
– ~30% smaller than ARM programs.
– ~30% faster when accessing 16-bit memory.
Thumb reduces 32-bit system to 16-bit cost:
– Consumes less power.
– Requires less external memory.
 Thumb
Traditional
32- 16- Thumb
bit bit ARM
uP uP
Memory 32-bit 16-bit 32-bit
Addressing

Integer 32-bit 16-bit 32-bit

Register Size

Instruction Size 32-bit 16-bit 16-bit

 Thumb … contd
Compressed subset of the 32-bit ARM instruction
set
– require lower bus bandwidth from narrow external
memory
– improves already outstanding code density
A Thumb enabled ARM
– executes both 32-bit ARM and 16-bit Thumb instructions
– allows runtime interworking between ARM and Thumb
code
– State change performed via Branch with eXchange (BX)
Instruction
Only the instructions are 16-bit
 ARM7TDMI-S™
Synthesizable RTL compliant
with the ARM7TDMI Custom Macrocell:
– Fully compatible with the ARMv4T architecture.
– Right denied to modify ARM7TDMI instruction set.
– Coprocessor interface allows custom functions to be added
outside core.
– EmbeddedICE support with “Multi- ICE” protocol converter or
third party device.
Supports AMBA interface:
– Standard interface, ideal for integration of the core into an ASIC
design.
Supports full-scan and automatic test pattern
generator.
 SecurCore™
Optimized processor family for smart
card solutions
– Security enhanced ARM7TDMI design
ARMv4T compliant
Low power, high performance
and small die size
– Memory Protection Unit (MPU)
– Anti-tampering/ counterfeiting measures
– JavaCard support
– Standard coprocessor interface for incorporation of
cryptographic solutions.
 SC100™ - Small synthesizable IP:
– 35K gates – 1 mm2 area
– 66 MHz* on 0.25 mm @2.5 V
– Power: 0.7 mW/ MHz
* Worst case: slow process, +125C, Vcc-10% depends on
synthesis tools, cell library and place route tools
The right core for the right solution