Input-Output

Organization
 Topics to be Covered
 Peripheral Devices
 Input-Output Interface
 Asynchronous Data Transfer
 Modes of Transfer
 Priority Interrupt
 Direct Memory Access (DMA)
 Peripheral Devices
Devices that are under the direct control of the computer are
said to be connected on-line.
Input or output devices attached to the computer are also
called peripherals.
Peripherals are electromechanical and electromagnetic devices

Video monitors are the most commonly used peripherals, most

popular one is a cathode ray tube (CRT).
The CRT contains an electronic gun that sends an electronic
beam to a phosphorescent screen in front of the tube.
This beam can be deflected horizontally and vertically.
A pattern on the screen is produced, using a grid that receives
a variable voltage to cause the beam to hit the screen and make
A characteristic feature of display devices is a cursor,
indicating a position for the next character to be inserted.
The cursor can be moved to any position in the screen, to a
single character, the beginning of a word, or to any line.
Edit keys are used to add or delete information based on the
cursor position.

The display terminal can operate in two modes:

- Single-Character Mode: All characters entered on the screen
through the keyboard are transmitted to the computer
simultaneously.
- Block mode: The edited text is first stored in a local
memory inside the terminal and then transferred to the
computer as a block of data.
 Printers provide a permanent record on paper of computer
output data or text.
There are three basic types of character printers:
- Daisywheel: Contains a wheel with the characters placed
along the circumference, the wheel rotates to the proper
position and an energized magnet then presses the letter
against the ribbon, to print character.
- Dot Matrix: Contains a set of dots along with the printing
mechanism. For example, a 5 x 7 dot matrix printer, prints
80 characters per line has seven horizontal lines, each
consisting of 5 x 80 = 400 dots. Each dot can be printed or
not, depending on the specific characters that are printed on
the line.
- Laser: Uses a rotating photographic drum to imprint the
character images, as a copying machine.
Magnetic tapes:
- High-speed rotational surfaces coated with magnetic
material
- Stores files of data
- Access is sequential, one after another as the tape moves
along a stationary read-write mechanism.
- Cheapest and slowest methods for storage
- Can be removed when not in use.

Magnetic Disks are used mostly for bulk storage of programs

and data.
 ASCII Alphanumeric Characters
The seven bits of the code are designated by b 1 through b7,
with b7, being the most significant bit (MSB).

The ASCII code contains:

- 94 Printing Characters
- 34 Nonprinting / Control Characters

The printing characters consist:

- 26 uppercase letters A through Z
- 26 lowercase letters a through z
- 10 numerals 0 through 9
- 32 special printable characters such as %, * , and $.
The 34 control characters are designated in the ASCII table
with abbreviated names along with functional names.
There are three types of control characters:
- Format Effectors: Control the layout of printing, such as
backspace (BS), horizontal tabulation (HT), and carriage
return (CR).
- Information Separators: Separate the data into divisions
like paragraphs and pages, such as record separator (RS)
and file separator (FS).
- Communication Control Characters: Useful during the
transmission of text between remote terminals, such as STX
(start of text) and ETX (end of text)
Additional 128 8-bit characters with the most significant bit
set to 1 are used for other symbols, such as the Greek alphabet
or italic type font. In data communication, the eighth bit can
be to indicate the parity of the binary-coded character.
 Input-Output Interface
Input-output interface facilitates transferring of information
between internal storage and external I/O devices.
Peripherals need special communication links for interfacing
them with the CPU.
The communication link resolves the following differences
between the central computer and each peripheral.
1. Peripherals are electromechanical and electromagnetic
devices and differ from the operation of the electronic
devices, CPU and memory. Hence, a conversion of signal
values may be required.
2. The data transfer rate of peripherals is usually slower than
the transfer rate of the CPU, so, a synchronization
mechanism may be needed.
3. Data codes and formats in peripherals differ from the word
format in the CPU and memory.
4. The operating modes of peripherals are different from each
other and each must be controlled so that it will not disturb the
operation of other peripherals connected to the CPU.
The I/O bus consists of:
- Data Lines
- Address Lines
- Control Lines.

Each peripheral device has associated with it an interface unit.

Each interface:
- Decodes the address and control received from the I/O bus
- Interprets them for the peripheral
- Provides signals for the peripheral controller
- Synchronizes the data flow
- Supervises the transfer between peripheral and processor
Each peripheral has its own controller, operates that particular
electromechanical device.
There are four types of commands that an interface may
receive:
- Control: Activates the peripheral and to inform it what to
do.
- Status: Test various status conditions in the interface and
the peripheral.
- Data Output: Causes the interface to respond by
transferring data from the bus into one of its buffer registers.
- Data Input: Causes the interface to respond by transferring
data from one of its registers into the bus.
 I/O versus Memory Bus
The processor along with I/O communication, also
communicates with the memory unit.
The memory bus also contains data, address, and read/write
control lines.
There are three ways that computer buses can be used to
communicate with memory and I/O:
1. Use two separate buses, one for memory and the other for
I/O.
2. Use one common bus for both memory and I/O but have
separate control lines for each.
3. Use one common bus for memory and I/O with common
control lines.
The computer has independent sets of data, address, and
control buses, one for accessing memory and the other for I/O,
with a separate I/O processor (IOP) along with CPU.
The memory communicates with both the CPU and the IOP
through a memory bus.
The IOP communicates also with the input and output devices
through a separate I/O bus with its own address, data and
control lines.
The purpose of the IOP is to provide an independent pathway
for the transfer of information between external devices and
internal memory.
 Isolated versus Memory-Mapped I/O
Many computers use one common bus to transfer information
between memory or I/O and the CPU.

The distinction between a memory transfer and I/O transfer is

made through separate read and write lines.

The I/O read and I/O write control lines are enabled during an
I/O transfer.
The memory read and memory write control lines are enabled
during a memory transfer.

This configuration isolates all I/O interface addresses from the

addresses assigned to memory and is referred to as the isolated
I/O method.
The CPU has distinct input and output instructions, and each is
associated with the address of an interface register.
Here, the CPU:
- Fetches and decodes the operation code of an input or
output instruction
- Places the address associated with the instruction into the
common address lines.
- Enables the I/O read (for input) or I/O write (for output)
control line.

Similarly, to fetch an instruction or operand, CPU:

- Places the memory address on the address lines
- Enables the memory read or memory write control line
The isolated I/O method isolates memory and I/O addresses,
as each has its own address space.

The other alternative is to use the same address space for both
memory and I/O, referred to as memory-mapped I/O
Here, the computers:
- Employ only one set of read and write signals
- Do not distinguish between memory and I/O addresses
- Treats an interface register as being part of the memory
system.
- Addresses assigned for interface registers cannot be used for
memory words, reducing the memory address range
 Asynchronous Data Transfer
In the interface, if the registers share a common clock with the
CPU registers, the transfer between the two units is said to be
synchronous.
But, in most cases, the internal timing in each unit is
independent as it uses its own private clock for internal
registers.
Hence, the two units are said to be asynchronous to each other.
In asynchronous data transfer, the control signals have to be
transmitted between two independent units to indicate the time
data transmission. There are two methods:
- Strobe Control
- Handshaking
 Strobe Control
The strobe control method employs a single control line to
time each transfer.
The strobe may be activated by either the source or the
destination unit. Hence, there are:
- Source-initiated data transfer / strobe
- Destination-initiated data transfer / strobe
 Handshaking
The disadvantages of the strobe method:
- The source unit that initiates the transfer has no way of
knowing whether the destination unit has actually received
the data item, placed in the bus.
- The destination unit that initiates the transfer has no way of
knowing whether the source unit has actually placed the
data on the bus.
These problems can be solved using the handshake method,
using a second control signal that provides a reply to the unit
that initiates the transfer.
 Asynchronous Serial Transfer
The transfer of data between two units, may be:
- Parallel
- Serial

In parallel data transmission, each bit of the message has its

own path and the total message is transmitted at the same time.
This means that an n-bit message must be transmitted through
n separate conductor paths.

In serial data transmission, each bit in the message is sent in

sequence one at a time.
For this, either one pair of conductors or one conductor and a
common ground are required.
Parallel transmission is faster but requires many wires. It is
used for short distances for speedy transmission.

Serial transmission is slower but is less expensive since it

requires only one pair of conductors.
Serial transmission can be:
- Synchronous
- Asynchronous

In synchronous transmission, the two units share a common

clock frequency and bits are transmitted continuously at the
rate dictated by the clock pulses.
In long distant serial transmission, each unit is driven by a
separate clock of the same frequency.
Synchronization signals are transmitted periodically between
the two units to keep their clocks in step with each other.
In asynchronous transmission, binary information is sent only
when it is available, otherwise the line remains idle.

But in synchronous transmission, the bits must be transmitted

continuously to keep the clock frequency synchronized.

In serial asynchronous data transmission technique, special

bits are inserted at both ends of the character code.
Hence, each character consists of three parts:
- A start bit is “0”
- The character bits
- Stop bits are “1”

The transmitter initially rests in the 1-state.

A transmitted character can be detected by the receiver using
the following transmission rules:
1 . With no character being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from
the start bit, i.e., “0”.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is
detected, as the line returns to the 1-state for at least one bit
time.
 Asynchronous Communication Interface
The CPU initiates operation of the asynchronous
communication interface by sending a byte to the control
register.
This initialization procedure places the interface in a Read /
Write mode of operation by defining certain parameters:
- The baud rate to use
- How many bits are in each character
- Whether to generate and check parity
- How many stop bits are appended to each character

Two bits in the status register are used as flags:

- One bit to indicate that the transmitter register is empty
- Another bit is to indicate that the receiver register is full.
The interface checks for any possible errors during
transmission and sets appropriate bits in the status register.

The CPU can read the status register at any time to check for
the occurrence of any errors.
There are three possible errors:
- Parity error: Occurs if the number of l's in the received data
is not the correct parity.
- Framing error: Occurs if the right number of stop bits is not
detected at the end of the received character.
- Overrun error: Occurs if the CPU does not read the
character from the receiver register before the next one
becomes available in the shift register.

Overrun error results in a loss of characters in the received

data stream.
 First-In, First-Out Buffer
A first-in, first-out (FIFO) buffer is a memory unit, storing the
information such that item first in is the item first out.
A FIFO buffer:
- Has separate input and output terminals
- Can input data and output data at two different rates
- Order of output data is always same as that of input data

If the source unit is slower than the destination unit, the buffer
can be filled with data at a slow rate and later emptied at the
higher rate.
If the source is faster than the destination, the FIFO buffer fills
out the source data arriving in bursts.
But the time between bursts is long enough for the destination
unit to empty some or all the information from the buffer.
It consists:
- Four 4-bit registers RI, I = 1, 2, 3, 4, i.e., for four words
- A control register with flip-flops Fi, i = 1, 2, 3, 4, one for
each register.
The number of bits per word can be increased by increasing
the number of bits in each register.
The number of words can be increased by increasing the
number of registers.

A flip-flop Fi in the control register consists:

- “1” indicating that a 4-bit data word is stored in the
corresponding register RI.
- “0” indicating that the corresponding register does not
contain valid data
 Modes of Transfer
Binary information:
- Received from an external device is usually stored in
memory for later processing.
- Transferred from the central computer into an external
device originates in the memory unit.
The CPU merely executes the I/O instructions and may accept
the data temporarily.

Data transfer between the central computer and I/O devices

may be handled in a variety of modes.
- Some modes use the CPU as an intermediate path;
- Others transfer the data directly to and from the memory
unit.
Data transfer to and from peripherals may be handled in one of
three possible modes:
- Programmed I/O
- Interrupt-initiated I/O
- Direct memory access (DMA)

In Programmed I/O:
- Operations are the result of I/O instructions written in the
computer program.
- Each data item transfer is initiated by an instruction.
- The transfer is to and from a CPU register and peripheral.
- Other instructions are needed to transfer the data to and
from CPU and memory.
- Transferring of data requires constant monitoring of the
peripheral by the CPU, thereby wasting the time.
In Interrupt-initiated I/O:
- The interface keeps monitoring the device and generates an
interrupt request to the CPU, as soon as the device is ready
for data transfer.
- Upon detecting the external interrupt signal:
 The CPU momentarily stops the task it is processing
 Branches to a service program to process the I/O transfer
 Returns to the task it was originally performing
In Direct Memory Access (DMA):
- The CPU
 Initiates the transfer by supplying the interface with the
starting address
 The number of words needed to be transferred
 Then proceeds to execute other tasks
The interface transfers data into and out of the memory unit
through the memory bus using DMA.
Example of Programmed I/O
 Interrupt-Initiated I/O
Instead of the CPU constantly monitoring the flag, the
interface inform the computer when it is ready to transfer data,
using an interrupt.
Now, the CPU deviates from what it is doing to take care of
the input or output transfer.
After the transfer is completed, the CPU resumes the task it
was doing before the interrupt.

For the interrupt, the CPU responds by:

- Storing the return address from the program counter into a
memory stack
- Control branches to a service routine that processes the
required I/O transfer.
There are two methods for choosing the branch address of the
service routine:
- Vectored Interrupt
- Non-vectored Interrupt

In a vectored interrupt, the source that interrupts supplies the

branch information to the CPU, called as interrupt vector.
An interrupt vector can be:
- The first address of the I/O service routine.
- An address that points to a location in memory where the
beginning address of the I/O service routine is stored.

In a non-vectored interrupt, the branch address is assigned to a

fixed location in memory.
 Software Considerations
Along with the hardware, a computer must also have software
routines for:
- Controlling peripherals
- Transfer of data between the CPU and peripherals
- Issuing control commands to activate the peripheral
- Checking the device status to determine the readiness for
data transfer
- Transferring item by item until the data is completed
- Error checking and other useful steps

In interrupt-controlled transfers, the I/O software must issue

commands to:
- The peripheral to interrupt when it is ready
- Service the interrupt when it occurs
In DMA transfer, the I/O software must initiate the DMA
channel to start its operation.

As the software for I/O is complex, I/O routines for standard

peripherals are provided by the manufacturer as part of the
operating system.
The user can refer the established routines to specify the type
of transfer required without going into the details
 Priority Interrupt
In general, a number of I/O devices are attached to the
computer, with each device being able to originate an interrupt
request.
So, the interrupt system has to:
- Identify the source of the interrupt
- Decide the device to be serviced first in case of multiple
interrupts

A priority interrupt is a system that establishes a priority over

the various sources to determine which request is to be
serviced first when two or more requests arrive simultaneously
The system may also determine which conditions are
permitted to interrupt the computer while another interrupt is
being serviced.
Higher-priority interrupt levels are assigned to requests which,
if delayed or interrupted, could have serious consequences.
Devices with high speed transfers such as magnetic disks are
given high priority, and slow devices such as keyboards
receive low priority.
When two devices interrupt the computer at the same time, the
computer services the device, with the higher priority first.
 Daisy-Chaining Priority
The daisy-chaining method consists of a serial connection of
all devices that request an interrupt.
The device with the highest priority is placed in the first
position, followed by lower-priority devices.
The device with the lowest priority is placed last in the chain.

The interrupt request line is common to all devices and forms

a wired logic connection.
If any device has its interrupt signal, the interrupt line goes to
the low-level state to enable the interrupt input in the CPU.
When no interrupts are pending, the interrupt line stays in the
high-level state and no interrupts are recognized by the CPU.
This is equivalent to a negative-logic OR operation.
 Parallel Priority Interrupt
The parallel priority interrupt method uses a register whose
bits are set separately by the interrupt signal from each device.
Priority is established according to the position of the bits in
the register.

The circuit may include a mask register whose purpose is to

control the status of each interrupt request.
The mask register can be programmed:
- To disable lower-priority interrupts during the service of a
higher-priority device
- To allow a high-priority device to interrupt the CPU while a
lower-priority device is being serviced.
 Interrupt Cycle
The interrupt enable flip-flop IEN can be set or cleared by
program instructions, ION and IOF, thus providing flexibility
for the programmer.
With IEN =0, the interrupt request coming from IST is
neglected by the CPU.

If IOF has been inserted in the program to clear IEN, it means

that the user does not want his program to be interrupted.
An ION instruction to set IEN indicates that the interrupt
facility will be used while the current program is running.

In most computers, internal hardware clears IEN to 0 every

time an interrupt is acknowledged by the processor.
At the end of each instruction cycle the CPU checks IEN and
the interrupt signal from IST.
- If either is equal to 0, control continues with the next
instruction.
- If both IEN and IST are equal to 1, the CPU goes to an
interrupt cycle.

During the interrupt cycle the CPU performs the following

sequence of microoperations:
SP  SP – 1 Decrement Stack Pointer
M[SP]  PC Push PC into Stack
INTACK  1 Enable Interrupt Acknowledge
PC  VAD Transfer Vector Address to PC
IEN  0 Disable Further Interrupts
Go to fetch next instruction
 Software Routines
Along with the hardware, a priority interrupt system must also
have software routines for:
- Servicing the interrupt requests
- Controlling the interrupt hardware registers

Each device has its own service program and can be reached
through a jump (JMP) instruction at the assigned vector
address
The symbolic name of each routine represents the starting
address of the service program.
The stack is used for storing the return address after each
interrupt.
 Initial and Final Operations
Each ISR must have an initial and final set of operations for
controlling the registers in the hardware interrupt system.

The initial sequence must have instructions to control the

interrupt hardware in the following manner:
1. Clear lower-level mask register bits.
2. Clear interrupt status bit IST.
3. Save contents of processor registers.
4. Set interrupt enable bit IEN.
5. Proceed with service routine.
The final sequence must have instructions to control the
interrupt hardware in the following manner:
1. Gear interrupt enable bit IEN.
2. Restore contents of processor registers.
3. Clear the bit in the interrupt register belonging to the source
that has been serviced.
4. Set lower-level priority bits in the mask register.
5. Restore return address into PC and set IEN.

The initial and final operations listed above are referred to as

overhead operations or housekeeping chores.
 Direct Memory Access (DMA)
The transfer of data between a fast storage device and memory
is often limited by the speed of the CPU.
Hence, letting the peripheral device manage the memory buses
directly, improves the speed of the transfer.
This technique is called as DMA, in this the CPU is idle and
has no control over the buses.
The DMA Controller takes over the buses to facilitate the
transfer between peripheral device and Memory.
The transfer by DMA can be in several ways, the two popular
ways are:
- Burst Transfer: A block sequence consisting of a number of
memory words is transferred as a continuous burst.
- Cycle Stealing: In this, DMA controller transfers one data
word at a time and returns the control of buses to the CPU.
DMA Controller
DMA Transfer