Chapter FOUR

Combinational Logic
Analysis and Design

DIGITAL LOGIC DESIGN

By Getahun n.
 Digital System
 The digital system consists of two types of circuits, namely
 Combinational Logic Circuits and
 Sequential Logic Circuits
 A combinational Logic Circuit:
 Consists of logic gates, where outputs are at any instant and are
determined only by the present combination of inputs.
 A Sequential Logic Circuits
 Contain logic gates as well as memory cells.
 And Their outputs depend on the present inputs as well as on the
states of memory elements.
 Combinational Logic Circuit
 A combinational logic circuit consists of input variables, logic gates,
and output variables.
 The logic gates accept signals from inputs and output signals are
generated according to the logic circuits employed in it
 Figure below shows a block diagram of a combinational logic circuit.
 There are n number of input variables coming from an electric source
and m number of output signals go to an external destination.
 Design Procedure OF Combinational Logic Circuit
 Any combinational circuit can be designed by the following steps of design
procedure.
1. State the problem.
2. Identify the number of input variables and output functions.
3. Assign the input and output variables with letter symbols.
4. Prepare the truth table which completely defines the relationship
between the input variables and output functions.
5. Obtain the simplified Boolean expression by using any method of
minimization - algebraic method, or Karnaugh map method.
6. Constructing a logic diagram for the simplified expression using logic
gates.
 The output Boolean functions from the truth table are simplified by any
available method, such as algebraic manipulation, the K-map method, or the
tabulation procedure.
 Design Constraints
 However, in any particular application, certain restrictions, limitations, and criteria
will serve as a guide in the process of choosing a particular algebraic expression.
 A practical design method would have to consider such constraints as
1. Minimum number of gates,
2. Minimum number of inputs to a gate,
3. Minimum propagation time of the signal through the circuit,
4. Minimum number of interconnections, and
5. Limitations of the driving capabilities of each gate.
 Since all these criteria cannot be satisfied simultaneously, and since the importance
of each constraint is dictated by the particular application, it is difficult to make a
general statement as to what constitutes an acceptable simplification.
 In most cases, the simplification begins by satisfying an elementary objective, such
as producing a simplified Boolean function in a standard form, and from that
proceeds to meet any other performance criteria.
 Half Adder
 Basic rules of binary addition are performed by a half adder, which
has two binary inputs (A & B) and two binary outputs (Cout and Sum)
 The inputs and outputs can be summarized on a truth table.
 The S(sum) represents the least significant bit of the sum.
 The Cout represents the most significant bit of the sum.
 The Boolean functions for the two output from the truth table:
 S = A’B + AB’ = A⊕B Inputs Outputs
A B Cout S
0 0 0 0
 Cout = AB 0 1 0 1
1 0 0 1
1 1 1 0
 The logic symbol and equivalent circuit are:
 Full Adder
 Full Adder has three binary inputs (A, B, and Carry in) and two
binary outputs (Carry out and Sum).
 Symbol

 The truth table summarizes the operation.

 The Boolean functions for the two output from the truth table:

Sum = A’B’C + A’BC’ + AB’C’ + ABC

Cout = A’BC + AB’C + ABC’ + ABC
 Full Adder
 Using x-OR,
S = A⊕ B⊕C and C out = AB + C(A⊕ B)
 A full-adder can be constructed from two half adders as shown:
 Parallel Adder
 Full adders are combined into parallel adders that can add binary numbers with
multiple bits.
 It consists of full-adders connected in a chain, with the output carry from each full-
adder connected to the input carry of the next full-adder in the chain.
 An n-bit parallel adder requires n full-adders. A 4-bit adder is shown as below.

 The output carry (C4) is not ready until it propagates through all of the full adders.
 This is called ripple carry, delaying the addition process.
 Parallel Adder
 Example:
a) What are the sum outputs when 111 and 101 are added by the 3-
bit parallel adder?
b) What are the sum outputs when 1110 and 1011 are added by the
4-bit parallel adder?
 Subtractor
 The subtraction of binary numbers can be done most conveniently by means
of 2’s complements.
 Remember that the subtraction A - B can be done by taking the 2's
complement of B and adding it to A.
 The 2's complement can be obtained by taking the 1's complement and
adding one to the least significant pair of bits. A 4-bit subtractor circuit is
shown.
 Parallel Adder and Subtractor
 The addition and subtraction operations can be combined into one circuit
with one common binary adder.
 This is done by including an exclusive-OR gate with each full adder.
 A 4-bit adder and subtractor is shown.
 Parallel Adder and Subtractor
 The mode input M controls the operation.
 When M = 0, the circuit is an adder, and
 when M = 1, the circuit becomes a subtractor.
 Each exclusive-OR gate receives input M and one of the inputs of B.
 When M = 0, we have B ⊕ 0 = B
 When M = 1, we have B ⊕ 1= B’ and Cin =1.
 Decoder
 A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines.
 If the n-bit decoded information has unused or don't-care combinations, the
decoder output will have fewer than 2n output.
 The decoders presented here are called n-to-2n-line decoders,
 Their purpose is to generate the 2n (or fewer) minterms of n input variables.
 The name decoder is also used in conjunction with some code converters
such as a BCD-to-decimal decoder.
 Only one output can be active (high) at any times.
 Decoder
 3x8 Decoder

b) Block diagram

a) Truth table
 Decoder
 3x8 Decoder
 Decoder With Enable Input
 Normally every commercially available decoder ICs have a special input
other than normal working input variables called ENABLE.
 The use of this ENABLE input is that when activated the complete IC
comes to the working condition for its normal functioning.
 If ENABLE input is deactivated the IC goes to sleep mode, the normal
functioning is suspended, and all the outputs become logic 0 irrespective of
normal input variables conditions.
 Its function is build higher decoder from lower decoders.

Figure: 2-to-4 decoder with enable input E.

 Decoder With Enable Input
 Example:- Construct a 3-to-8 line decoder with the use of a 2-to-4
line decoder.

 Example:- Construct a 4-to-16 line decoder with the use of a 2-to-4

line decoder.
 Example:- Construct a 5-to-32 line decoder with the use of a 3-to-8
line decoder.
 Encoder
 An encoder is a digital circuit that performs the inverse operation of
a decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
 The output lines generate the binary code corresponding to the
input value.
 It is assumed that only one input has a value of 1 at any given
time; otherwise the circuit has no meaning.
 Encoder
 8x3 Encoder:

 The encoder can be implemented with OR gates whose inputs are

determined directly from the truth table.
 Encoder
 These conditions can be expressed by the following output Boolean
functions:

 Logic circuit from the above Boolean function will be:

 Multiplexer
 Multiplexer is also called data selectors.
 A digital multiplexer is a combinational circuit that selects binary
information from one of the 2n input channels and transmits to a single
output line.
 The selection of the particular input channel is controlled by a set of select
inputs.
 It select binary information from one of many input lines and direct it to a
single output line
 2n input lines needs n selection lines and one output line
 Multiplexer
 2-to-1-line multiplexer:
 Multiplexer
 4x1-line Multiplexer:
 A 4x1 Multiplexer has four data inputs I 3, I2, I1 & I0, two selection lines
s1 and s0 and one output Y.
 The block diagram of 4x1 Multiplexer is shown in the following
figure.

Fig. : block diagram of

4x1 Mux.
 Multiplexer
 A logic circuit, for 4x1 multiplexer will be:

Fig. : Logic circuit of

4x1 Mux.
 Multiplexer with enable inputs
 As in decoders, multiplexer ICs may have an enable input to control the
operation of the unit.
 When the enable input is in a given binary state, the outputs are disabled,
and when it is in the other state (the enable state), the circuit functions as a
normal multiplexer.
 The enable input (sometimes called strobe) can be used to expand two or
more multiplexer ICs to a digital multiplexer with a larger number of inputs.
Multiplexer with enable inputs
 Example:- Construct a 8-to-1 multiplexer with the use of a 4-to-1 line
multiplexer and external gate.

 Example:- Construct a 16-to-1 multiplexer with the use of only a 4-

to-1 line multiplexer.
 De-Multiplexer
 A de-multiplexer is a circuit that receives information from a single
line and directs it to one of 2n possible output lines.

 The selection of a specific output is controlled by the bit combination

of n selected lines.

 The term “demultiplex” means one into many.