Lecture-12
System Verilog - Data
types
Data Types
• SystemVerilog offers many improved data structures compared with
Verilog.
• Some of these were created for designers but are also useful for
testbenches.
• In this chapter you will learn about the data structures most useful for
verification.
Data Types
• SystemVerilog offers many improved data structures compared with
Verilog.
• Some of these were created for designers but are also useful for
testbenches.
• In this chapter you will learn about the data structures most useful for
verification.
Data Types
• SystemVerilog offers many improved data structures compared with
Verilog.
• Some of these were created for designers but are also useful for
testbenches.
• In this chapter you will learn about the data structures most useful
for verification.
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same
data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same
data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same
data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• SystemVerilog introduces new data types with the following benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built-in support for searching and sorting
• Unions and packed structures: allows multiple views of the same
data
• Classes and structures: support for abstract data structures
• Strings: built-in string support
• Enumerated types: code is easier to write and understand
Data Types
• Verilog-1995 has two basic data types: variables (reg) and nets, that hold
four-state values: 0, 1, Z, and X. RTL code uses variables to store
combinational and sequential values.
• Variables can be unsigned single or multi-bit (reg [7:0] m), signed 32-bit
variables (integer), unsigned 64-bit variables (time), and floating point
numbers (real).
• Variables can be grouped together into arrays that have a fixed size. All
storage is static, meaning that all variables are alive for the entire
simulation and routines cannot use a stack to hold arguments and local
values.
• A net is used to connect parts of a design such as gate primitives and
module instances. Nets come in many flavors, but most designers use
scalar and vector wires to connect together the ports of design blocks.
• SystemVerilog adds many new data types to help both hardware designers
and verification engineers.
Data Types
• Verilog-1995 has two basic data types: variables (reg) and nets, that hold
four-state values: 0, 1, Z, and X. RTL code uses variables to store
combinational and sequential values.
• Variables can be unsigned single or multi-bit (reg [7:0] m), signed 32-bit
variables (integer), unsigned 64-bit variables (time), and floating point
numbers (real).
• Variables can be grouped together into arrays that have a fixed size. All
storage is static, meaning that all variables are alive for the entire
simulation and routines cannot use a stack to hold arguments and local
values.
• A net is used to connect parts of a design such as gate primitives and
module instances. Nets come in many flavors, but most designers use
scalar and vector wires to connect together the ports of design blocks.
• SystemVerilog adds many new data types to help both hardware designers
and verification engineers.
Stack
• A stack is a special area of computer's memory which stores
temporary variables created by a function.
• In stack, variables are declared, stored and initialized during
runtime.
• It is a temporary storage memory. When the computing task is
complete, the memory of the variable will be automatically erased.
• The stack section mostly contains methods, local variable, and
reference variables.
Heap
• The heap is a memory used by programming languages to store
global variables.
• By default, all global variable are stored in heap memory space. It
supports Dynamic memory allocation.
• The heap is not managed automatically for you and is not as tightly
managed by the CPU. It is more like a free-floating region of
memory.
Data Types
• Verilog-1995 has two basic data types: variables (reg) and nets, that hold
four-state values: 0, 1, Z, and X. RTL code uses variables to store
combinational and sequential values.
• Variables can be unsigned single or multi-bit (reg [7:0] m), signed 32-bit
variables (integer), unsigned 64-bit variables (time), and floating point
numbers (real).
• Variables can be grouped together into arrays that have a fixed size. All
storage is static, meaning that all variables are alive for the entire
simulation and routines cannot use a stack to hold arguments and local
values.
• A net is used to connect parts of a design such as gate primitives and
module instances. Nets come in many flavors, but most designers use
scalar and vector wires to connect together the ports of design blocks.
• SystemVerilog adds many new data types to help both hardware designers
and verification engineers.
Data Types - Logic Types
• When to use reg and wire data type?
• SystemVerilog improves the classic reg data type so that it can be
driven by continuous assignments, gates and modules, in addition to
being a variable.
• It is given the new name logic so that it does not look like a register
declaration.
• The one limitation is that a logic variable cannot be driven by multiple
drivers such as when you are modeling a bidirectional bus.
• In this case, the variable needs to be a net-type such as wire.
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate, q is input to the ‘not’ gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate, q is input to the ‘not’ gate
my_dff d1(q, d, clk, rst_l); // d is driven by module, q is output of d1 ff
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Example: Using the logic data type
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk <= 0; // Procedural assignment
forever #(CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h; // Continuous assignment
not n1(q_l, q); // q_l is driven by gate
my_dff d1(q, d, clk, rst_l); // d is driven by module
endmodule
Thank You
Data Types
Type Mode State Size Sign?
bit
Bit[x:0]
byte
shortint
int
longit
logic
reg
integer
time
real
Verilog Tutorial and Lab (iitk.ac.in)
Xilinx ISE Four-Bit Adder in Verilog - dftwiki (smith.edu)
