Computer Organization

and Assembly Language

Lecture # 01
Introduction – Top Level View
Computer System Functions
Architecture & Organization 1
• Architecture is those attributes visible to
the programmer
—Instruction set, number of bits used for data
representation, I/O mechanisms, memory
addressing techniques.
—e.g. Is there a multiply instruction?
• Organization is how features are
implemented
—Control signals, interfaces between the
computer and peripherals, memory
technology.
—e.g. Is there a hardware multiply unit or is it
done by repeated addition?
Architecture & Organization 2
• All Intel x86 family share the same basic
architecture
• The IBM System/370 family share the
same basic architecture
• This gives code compatibility
—At least backwards (IBM System/360 family)
• Organization differs between different
versions
• Microcomputers – the relationship
between architecture and organization is
very close
— Reduced Instruction Set Computer (RISC)
Structure & Function
• Structure is the way in which components
relate to each other
• Function is the operation of individual
component as part of the structure
Function
• Basic functions that a computer can
perform are:
—Data processing
—Data storage
—Data movement
—Control
Functional View (figure 1.1)
Operations (a) Data movement (figure 1.2)
Operations (b) Storage (figure 1.2)
Operation (c) Processing from/to storage
(figure 1.2)
Operation (d)
Processing from storage to I/O (figure 1.2)
 Structure - Top Level (figure 1.4)

Peripherals Computer

Central
Processing Main
Unit Memory
“Processor”
Computer
• Storage System
• Processing
Interconnection
“System Bus”

Input
Output
Communication
lines
Structure - The CPU (figure 1.4)

CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal Bus
Memory

Control
Unit
Structure - The Control Unit (figure 1.4)

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
Review Questions
• What, in general terms, is the distinction
between computer organization and
computer architecture?
• Explain the functional view of a computer
with the help of flow chart.
• What are the four main functions of a
computer?
• Explain with a neat diagram the internal
structure of computer.
• List and briefly define the main structural
components of a processor.
von Neumann/Turing
• Stored-program concept referred to as the IAS
computer
• Main memory – which stores both data and
instructions
• Arithmetic and Logic Unit – capable of operating
on binary data
• Control unit – interprets instructions in memory and
causes them to be executed
• Input and output – equipment operated by control
unit
• Princeton Institute for Advanced Studies
—IAS
• Completed 1952
• Prototype of all general-purpose computers
Structure of von Neumann machine (IAS
Computer)

CA: Central Arithmetical

CC: Central Control
IAS - details
• 1000 storage locations – words of 40 bits
—Both data and instructions are stored
—Binary number
—Each number is represented by a sign bit and
a 39-bit value
—2 x 20 bit instructions
– An 8-bit opcode & a 12-bit address of the word in
memory (numbered from 0 to 999)
IAS Memory Formats
IAS - details
• Control unit operates the IAS by fetching
instructions from memory and executing
them one at a time
• Set of registers (storage in CPU)
—Memory Buffer Register (MBR)
—Memory Address Register (MAR)
—Instruction Register (IR)
—Instruction Buffer Register (IBR)
—Program Counter (PC)
—Accumulator (AC)
—Multiplier Quotient (MQ)
Structure of IAS –
detail
Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction Register
(IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• An instruction’s execution may involve
combination of above actions
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
• Mechanism by which other modules (e.g.
I/O, memory) may interrupt normal
sequence of processing
• Program
— e.g. arithmetic overflow, division by zero, attempt to
execute an illegal machine instruction
• Timer
— Generated by internal processor timer
— Allows the operating system to perform certain
functions on a regular basis
• I/O
— from I/O controller, to signal normal completion of an
operation, request service from the processor
• Hardware failure
— e.g. power failure or memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) - State
Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Interconnection Structures
• All the units must be connected
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
Computer Modules
Bus Interconnection
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• Point-to-Point interconnection structures
with packetized data transfer
What is a Bus?
• A communication pathway connecting two
or more devices
• A shared transmission medium
• Multiple communication lines
—Single line transmitting signals representing
binary 1 & 0
—Sequence of binary digits can be transmitted
across a single line
—Several lines can be used to transmit binary
digits in parallel
– An 8-bit unit of data can be transmitted over eight
bus lines
System Bus
• Connects major computer components
(processor, memory, I/O)
• Bus structure
—Fifty to hundreds of separate lines
—A particular function assigned to a line
– Three functional groups
+ Data lines
+ Address lines
+ Control lines
—Power distribution lines that supply power to
the attached modules
Data Lines
• Moving data among system modules
—No difference between “data” and
“instruction” at this level
• Collectively called Data Bus
• Number of lines referred to as the Width of
data bus
—8, 16, 32, 64 bit
—A key to determine system performance
Address Lines
• Identify the source or destination of data
• e.g. CPU needs to read an instruction
(data) from a given location in memory
• Address bus width determines maximum
memory capacity of system
—e.g. 8080 has 16 bit address bus giving 64k
address space
• Also used to address I/O ports
—Higher-order bits used to select a particular
module
—Lower-order bits used to select a memory
location or I/O port within the module
Control Lines (1)
• Control the access to and the use of the
data and address lines
• Control signals transmit both command
and timing information
—Timing signals
– Indicate the validity of data and address information
—Command signals
– Specify operations to be performed
Control Lines (2)
• Memory write/Memory read
• I/O write
• I/O read
• Transfer ACK
• Bus request
• Bus grant
• Interrupt request/Interrupt ACK
• Clock
• Reset
Bus Interconnection Scheme
Physical Realization of Bus Architecture
Single Bus Problems
• Performance will suffer if more devices are
connected to the bus
—Propagation delays
– More devices attached to the bus, the greater the
bus length and hence the greater the propagation
delay
—Aggregate data transfer demand approaches
the capacity of the bus
• Most systems use multiple buses to
overcome these problems
Traditional bus structure
High Performance Bus architecture
Bus Types
• Dedicated
—Separate data & address lines
• Multiplexed
—Shared lines
—Address valid or data valid control line
—Advantage - fewer lines
—Disadvantages
– More complex circuitry
– Reduce performance
Physical Dedication
• Use of multiple buses
—Each connects only a subset of modules
—I/O bus to interconnect all I/O modules
—Advantage – high throughput
—Disadvantage – increased size and cost
Bus Arbitration
• More than one module may need control
of the bus
• Only one module can transmit over bus at
one time
• Arbitration may be centralised or
distributed
Centralised or Distributed Arbitration
• Centralised
—Single hardware device for allocating time on
the bus
– Bus Controller
– Arbiter
—May be part of CPU or separate
• Distributed
—Each module contains access control logic
—Modules act together to share the bus
Timing
• Co-ordination of events on bus
• Synchronous
—Events determined by clock signals
—Control Bus includes clock line
—A single 1-0 is a bus cycle
—All devices can read clock line
—Usually sync on leading edge
—Usually a single cycle for an event
Synchronous Timing Diagram
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
Elements of Bus Design
Review Questions
• What general categories of functions are specified by computer
instructions?
• Explain the working of synchronous bus operations with a timing
diagram.
• List and briefly define two approaches to deal with multiple
interrupts.
• Briefly explain the Bus Interconnection Scheme.
• What is the benefit of using a multiple-bus architecture compared
to a single-bus architecture?
• What are the different classes of interrupts?
• List the different elements of bus design.
• What types of transfers must a computer’s interconnection
support?