Computer Architecture & Assembly

Language

CSC-250
COURSE LECTURE

COMPUTER SCIENCE DEPARTMENT

SIBAU KANDHKOT CAMPUS
What is a program?

A sequence of steps
arithmetic or logical
operation is done

a different set of
control signals is needed
Function of Control Unit
• A unique code for each operation
• Example: ADD, MOVE

Accept codes
Hardware Issues control
Segment signals
Computer Components
Compute PC = Program
Central Processing Unit (CPU) Counter
r
PC MAR System IR = Instruction
Main Memory
Bus .. Register
IR MBR .
0 MAR = Memory
I/O AR Instruction 1 Address Register
Execution 2
Unit Instruction MBR = Memory
I/O BR .. .
. . Buffer Register
Data . I/O AR =
I/O Module Data Input/Output
Address Register
..
.. . I/O BR =
Input/Output
Buffers Buffer Register
Fetch Cycle

Program
Instruction
Counter Processor Processor
Register (IR)
(PC)
• Holds address • Fetch • Load the • Interprets
of next instruction from instruction instruction
instruction to memory • Perform
fetch location pointed required actions
to by PC
• Increment PC
Execute Cycle
Processor I/O

Processor - Execution Data Processing

Memory
Cycle

Control
Addition Program Execution -
Example
Instruction Cycle State Diagram

Instruction Operand Operand

Fetch Fetch Store
Multiple
Results
Multiple
Operands

Instruction Instruction Operand Operand

Data
Address Operation Address Address
Operation
Calculation Decoding Calculation Calculation

Instruction complete, Fetch Return for string or

next instruction vector data
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing
Classes of Interrupts
• Program
• Stack overflow, division by zero
• Timer
 Generated by internal processor timer
 Used in pre-emptive multi-tasking
• I/O
• I/O controller – signal the error condition
• Hardware failure
• Power failure
Interrupt – Program Flow Control
Interrupt Cycle
• Added to instruction cycle
Fetch cycle Execution cycle Interrupt cycle

Interrupts
disabled
Check for
Fetch Next Execute
Start interrupt; process
Instruction Instruction Interrupts
interrupt
enabled

Halt
Interrupt Cycle (Cont.)
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
• Suspend execution of current program
• Save context
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore context and continue interrupted program
Transfer of Control via Interrupts
Multiple Interrupts - Approaches
• Disable interrupts
• Processor - ignore that interrupt request signal
• Situation: executing the program and interrupt occurs – interrupts are disable
immediately
• Pending - checked after the processor has enabled interrupts
• After interrupt handler routine completes
• Enable interrupts before resume
• Check additional interrupt
• Handle interrupt in strict sequential order
Multiple Interrupts – Sequential
Interrupt Processing
Multiple Interrupts – Nested
Interrupt Processing
Multiple Interrupts – Approaches
(Cont.)
• Define priorities
• Low priority interrupts can be interrupted by higher priority interrupts
• When higher priority interrupt has been processed, processor returns to
previous interrupt
Time Sequence of Multiple
Interrupts - Example
Interconnection Structures
• Collection of paths connecting the various modules
• Modules:
• Memory
• Processor
• I/O module
Modules: Major Form of Input and
Output - Memory
• Word of data - Read from
or written into the
memory
• Assigned a unique
numerical address
• Nature of the operation –
indicated by read and
write control signals
• Address – specify the
location for the operation
Modules: Major Form of Input and
Output - Processor
• Reads instruction and
data
• Writes out data (after
processing)
• Sends control signals to
other units
• Receives (& acts on)
interrupts
Modules: Major Form of Input and
Output – I/O Module
• Operations;
• Read
• Write
• Control more than one
external device
• External data path –
input and output of data
• Send interrupt signals to
CPU
Modules:
Major Form of Input and Output
Types of Transfers
• Memory to processor: Processor reads instruction/data from memory
• Processor to memory: Processor writes data to memory
• I/O to processor: Processor reads data from I/O device (via I/O
module)
• Processor to I/O: Processor sends data to I/O device
• I/O to/from memory: allowed to exchange data using Direct Memory
Access (DMA) – exclude processor
Bus Interconnection
• Communication pathway connecting two or more devices
• Key characteristic: shared transmission medium
• Consists of multiple communication pathways/lines
• Lines – transmit signals representing binary 1 and 0 – one data at a time
System Bus
• A bus that connects major computer components (CPU, memory, I/O)
• Computer interconnection structures – use one or more system buses
• Consists of 50 to hundreds of separate lines
• Each line – function. E.g: power
Data Line
• Provide a path for moving data among system modules
• Collective – data bus
Data Bus
• Collective of data lines
• Width of the data bus - Number of lines;
• 32, 64, 128 …
• Key factor in determining overall system performance
• Number of data lines – represents number of data can be transferred
at a time
Address Lines
• Designate the source or destination of the data on data bus
Address Bus
• Collective of address lines
• Width of the address bus determines the maximum possible memory
capacity of the system
Control Lines
• Used to control the access to and the use of the data and address
lines
• Control signals transmit both command and timing information
among system modules
• Command signals – specify operations to be performed
• Timing signals – validity of data and address information
Bus Interconnection Scheme
Operation of the Bus
• Send data
• Obtain the use of the bus
• Transfer data via the bus
• Request data
• Obtain the use of the bus
• Transfer a request to the other module over appropriate control and address
lines
System Bus - Physical
• Number of parallel electrical
conductors – metal lines on the
circuit board
Physical Realization of Bus
Architecture
Single Bus - Problem
• Many of devices on one bus leads to:
• Propagation delays
• Long data paths mean that co-ordination of bus use can adversely affect performance
• If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome these problems
Types of Bus
• Dedicated
• Separate data & address lines
• Multiplexed
• Shared lines
• Address valid or data valid control line
• Advantage
• Fewer lines
• Disadvantages
• More complex control
• Reduction in performance
Bus Arbitration
• Process of insuring only 1 devices places information onto the bus at a
time
• Master - slave mechanism
• Master is given control of the bus and can place information onto it
• Slave receives the information from the master
• Two methods
• Centralized
• Decentralized
Master–Slave Mechanism: Methods
• Centralized
• Central bus controller mediates all device requests for the bus
• May be part of CPU or a hardware of its own (arbiter)
• Decentralized
• No centralized controller
• All devices contain logic to control access to the bus
Bus Timing
• Synchronous
• Occurrence of events on the bus is determined by the clock
• All events start at the beginning of a clock cycle
• Example: PCI bus (Peripheral Component Interface bus
• Asynchronous
• The occurrence of one event follows and depends on the occurrence of a
previous event
• More flexible than synchronous bus but more complicated as well
• Accommodates wider range of device speeds
• Example: Future bus+
Assignment for Reading

• Traditional (ISA) VS High Performance Bus Structure