Unit II
Unit II
&
Opamp
C
C
Collector
N Collector Base
Junction JC
P B
B
Emitter Base Base
Junction JE
N
E
Emitter
E
npn pnp
E n p n C E p n p C
Normally Emitter layer is heavily doped, Base layer is lightly doped and Collector
layer has Moderate doping.
February 13, 2025 7
transistor currents
Collector Base
Junction JC
P B
B
Emitter Base Base
Junction JE
N
E
Emitter
E
E
Emitter
N E
B P B
Base
N C
C
Collector
Base
Junction Junction
JEB JCB
+ - - - - +
+ - - - - +
Emitter collector
+ - - - - +
N P N
+ - - - - +
+ - - - - +
Depletion Depletion
region region
February 13, 2025 10
Transistor biasing in the active region
P N P
Emitter collector
N P
holes emitted
holes collected
RE RC
conventional
current
-
+ + -
Base
Conventional
current
February 13, 2025 VEE IE = IC + IB VCC 12
Transistor configuration
• Depending on which terminal is made common to input and
output port there are three possible configurations of the
transistor. They are as follows:
Emitter collector
N P N
Electron emitted
Electron collected
Emitter electron
current
February 13, 2025 VEE VCC 14
Transistor operation in the active region N-P-N
common base configuration
JEB JCB
+ - - - - +
+ - - - - +
Emitter collector
+ - - - - +
N N
+ - - - - +
+ - - P - - +
Depletion Depletion RC
region region
ICBO is a reverse saturation IC=ICBO
VCC
Current flowing due to the +
Base -
Minority carriers between
Collector and base when the
Emitter is open. ICBO flows due to the reverse ICBO
Biased collector base junction. Is a collector to base leakage current
February 13, 2025 15
ICBO is neglected as compared to IC With open emitter
Current relations in CB configuration
IC = IC(INJ) + ICBO
αdc = IC(INJ) / IE
IC(INJ) = αdc IE
IC = αdcIE + ICBO
- +
RE VBE JE JC
+ VCB =8V ΔIE
- + -
B
VEE
IE VBE
E C ΔVBE
- +
VBE Input resistance
RE
VCB =8V Ri = ΔVBE / ΔIE
+
- + -
As the change in emitter current is very large for a
February 13, 2025 B Small change in input voltage, the input resistance
17
VEE Ri is small
Characteristics of a transistor in CB configuration
“Early effect” or “base width modulation”.
JE JC
- - - - - - +
- - - - - - +
Emitter collector
- - -
Base - - - +
Emitter Collector
N P- - - - - - + N
- - - - - - +
For extremely large VCB the effective base width may be reduced to zero,
causing voltage breakdown of a transistor.
This phenomenon is known as punch through
February 13, 2025 18
Characteristics of a transistor in CB configuration
Output characteristics
IC Active region
Constant
IE=3mA
(mA) (high output dynamic
C
E N P N IC resistance)
+ 3 IE=3 mA
RE JE JC VCB RC 2 IE=2 mA
- + - + 1 IE=1 mA
IC=ICBO
IE=0
B
VEE VCC
-1 0 5 10 VCB
IC (mA)
VCB constant
4
0 1 2 3 4
IE (mA)
α dc = ΔIC / ΔIE
February 13, 2025 20
Characteristics of a transistor in CE configuration
Input characteristics
C
•It is a graph of input current (IB)
IC
versus input voltage (VBE) at a constant
output voltage (VCE). N
IB
(μA) VCE
VCE = 4V 10V constant
IB JC +
P
B VCC
ΔIB JE
-
Ri=ΔVBE/ΔIB RB VBE
ΔVBE
N
VCE Constant +
VBB
0 0.7 1 2 IE
VBE
- E
The value of dynamic input resistance “Ri”
February 13, 2025 N-P-N Transistor 21
is low for CE
Characteristics of a transistor in CE
configuration
Output characteristics
• It is a graph of output current (Ic)
versus output voltage (VCE) at a C
IC
constant input current (IB)
βdc = IC /IB RE
Saturation Active
region region
IC IB = 4μA
+
(mA)
4 B
IB = 4μA
3
IB = 3μA VBE VCE -
RB VCC
2
IB = 2μA
VBB + IE
1 IB = 0
1 2 3 4 E
VCE -
N-P-N Transistor
February 13, 2025 Cutoff region 22
Characteristics of a transistor in CE configuration
Transfer characteristics
IC (mA)
VCE constant
4
0 1 2 3 4
IB (μA)
β ac = ΔIC / ΔIB
DC load line
IC +
(mA)
IC
(MAX)
A -
IB = 4μA VCE VCC
3
IB = 3μA
2
IB = 2μA
1 IB = 0 E
VCE
1 2 3 4 B N-P-N Transistor
February 13, 2025 VCE=VCC 26
February 13, 2025 27
Typical Junction Voltages
Voltage Silicon Transistor Germanium Transistor
VBE (Cut-off) 0 -0.1V
•Fixed bias
•Collector-to-base bias
•Self Biased or Voltage divider bias
•Fixed bias with emitter resistor
•Emitter bias
R2 RE CE
MOSFET was
invented by
Atalla & Dawon
at Bell Labs in
195913, 2025
February 37
Linear & Saturation Regions
Inverting input 2
- 7
6 Output
741
3
+
Non-Inverting input 4
Thomas L. Floyd
February
Electronic 13,6e2025
Devices, and Electronic 46
Devices: Electron Flow Version, 4e
Manufactures of OP-AMP IC 741
• The manufactures of Op-amp ICs are companies
like Fairchild, National semiconductor, Motorola,
Texas Instruments and signetics.
Ideal
Vd Differential
Amplifier Vo = V1 – V2
+ +
V1 V2
- -
V1 V2
- -
Differential gain -
• Vo = Ad ( V1 – V2 )
Where Ad is called as the differential gain.
• The differential gain can be defined as the gain with which the
differential amplifier amplifies the differential signal.
Vo = Ad Vd as Vd = V1 – V2
Gain Ad = Vo / Vd
Ad (dB) =10 log10 [ Vo / Vd ]
February 13, 2025 49
Ideal
Vd Differential
Amplifier Vo = V1 – V2
+ +
V1 V2
- -
+VCC
input
Inverting input
2
- 7
6 Vo
741
3
+
4
Inverted Output signal
-VEE
+VCC
2
- 7
6 Vo
741
3
+
input Non-Inverting
4
input Non-Inverted Output signal
-VEE
V1 V2
- -
+ VCC
Inverting input
-
Ro Output
Vd Ri
+ +
AVVd
+ Vo RL
-
Non-Inverting input
-
-VEE
8
Ri
IB2= 0
- Ro 0
V2
8
V
IB1= 0
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
5. Infinite Bandwidth
Bandwidth of an amplifier is the range of frequencies over which all
the signal frequencies are amplified almost equally.
The bandwidth of an ideal Op-amp is infinite. So it can amplify any
frequency from zero to infinite hertz.
Thus the gain of an ideal amplifier is constant from zero to infinite hertz.
February 13, 2025 61
The ideal OP-AMP
Ri
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
. Infinite CMRR
for an Op-amp, the common mode rejection ratio (CMRR) id defined
as the ratio of differential gain to common mode gain.
CMRR is infinite for the ideal Op-amp.
hus the output voltage corresponding to the common mode noise is zero.
February 13, 2025 62
The ideal OP-AMP
Ri
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
8
IB2= 0
- Ro 0
V2
8
V
IB1= 0
8
3 Voltage gain Av 2 X 105
4 Bandwidth BW 1 MHz
8
5 CMRR 90 dB
8
8
6 Slew rate S 0.5 V/μS
7 Input offset voltage 2 mV 0
8
8 PSRR 150 μV/V 0
9 Input bias current 50 nA 0
10 Input offset current 6 nA 0
February 13, 2025 65
Open loop configuration of OP-AMP
• The meaning of open loop operation is that there is
absolutely no feedback present from the output to input.
Vo = Av Vd
+V(SAT)
-
a b
Vd Op amp 0
+ Vd
+ + Vo = Av Vd
1
V2 -V(SAT)
- -
• Types of feedback
Positive feedback or Regenerative feedback
Negative feedback or Degenerative feedback.
Feedback resistor
input
Output
V2 2
-
6 Vo
OP-AMP
V1 3
+
February 13, 2025 72
Advantages of Negative feedback
• Negative feedback is used in the amplifier circuits as they
provide the following improvements in the operation of an
amplifier:
Ri +VCC
8
I=0
V2 -
Output
Vd Ri Vo = AVVD
+
V1
-VEE
8
0
-
8
+ VO
VS t
0
-
8
V2
-
I2 = 0
OP-AMP
I1 = 0
Vo
V1 + AV =
8
+
VS