CHAPTER-II

Computer Arithmetic
• 1. Addition and Subtraction
• 2. Multiplication Algorithms
• 3. Division Algorithms
• 4. Floating Point Arithmetic Operations
• 5. Decimal Arithmetic Unit
• 6. Decimal Arithmetic Operations
• In this chapter we develop the various arithmetic
algorithms and show the procedure for
implementing them with digital hardware.
• We consider addition, subtraction, multiplication,
and division for the following types of data:
• 1. Fixed-point binary data in signed-magnitude
representation
• 2. Fixed-point binary data in signed-2's complement
representation
• 3. Floating-point binary data
• 4. Binary-coded decimal (BCD) data
1. Addition and Subtraction
• fixed-point binary numbers: signed-magnitude,
signed-l's complement, or signed-2‘s complement.
• Most computers use the signed-2's complement
representation when performing arithmetic
operations with integers.
• For floating-point operations, most computers use
the signed-magnitude representation for the
mantissa.
• In this section we develop the addition and
subtraction algorithms for data represented in
signed-magnitude and again for data represented in
signed-2's complement.
Addition and Subtraction with Signed-Magnitude Data:
• We designate the magnitude of the two numbers by A and B.
• When the signed numbers are added or subtracted, we find
that there are eight different conditions to consider,
depending on the sign of the numbers and the operation
performed.
• These conditions are listed in the first column of Table 10-
1.
• The other columns in the table show the actual operation to
be performed with the magnitude of the numbers.
• The last column is needed to prevent a negative zero.
• In other words, when two equal numbers are subtracted, the
result should be +0 not -0.
Hardware Implementation:
• To implement the two arithmetic operations with
hardware, it is first necessary that the two numbers be
stored in registers.
• Let A and B be two registers that hold the magnitudes
of the numbers, and A, and B, be two flip-flops that
hold the corresponding signs.
• The result of the operation may be transferred to a
third register:
• However, a saving is achieved if the result is
transferred into A and AS,.
• Thus A and AS, together form an accumulator register.
• First, a parallel-adder is needed to perform
the micro operation A + B .
• Second, a comparator circuit is needed to
establish if A > B, A = B, or A < B.
• Third, two parallel-subtractor circuits are
needed to perform the micro operations A - B
and B - A.
• The sign relationship can be determined from
an exclusive OR gate with A, and B, as inputs.
• It consists of registers A and B and sign flip-flops
A, and B, .
• Subtraction is done by adding A to the 2' s
complement of B.
• The output carry is transferred to flip-flop E, where
it can be checked to determine the relative
magnitudes of the two numbers.
• The add-overflow flip-flop AVF holds the overflow
bit when A and B are added.
• The A register provides other micro operations that
may be needed when we specify the sequence of
steps in the algorithm.
• The addition of A plus B is done through the parallel adder.
• The S (sum) output of the adder is applied to the input of the A
register.
• The complementer provides an output of B or the complement
of B depending on the state of the mode control M.
• The complementer consists of exclusive-OR gates and the
parallel adder consists of full-adder circuits as shown in Fig.
4-7 in Chap. 4.
• The M signal is also applied to the input carry of the adder.
• When M = 0, the output of B is transferred to the adder, the
input carry is 0, and the output of the adder is equal to the sum
A + B.
• When M a I, the l's complement of B is applied to the adder,
the input carry is I, and output S = A + B + 1.
• This is equal to A plus the 2's complement of B, which is
equivalent to the subtraction A - B.
Hardware Algorithm:
• The two signs A, and B,are compared by an exclusive-OR
gate.
• If the output of the gate is O, the signs are identical; if it is I,
the signs are different For an add operation,
• identical signs dictate that the magnitudes be added.
• For a subtract operation, different signs dictate that the
magnitudes be added.
• The magnitudes are added with a micro operation EA .-A + B.
• where EA is a register that combines E: and A.
• The carry in E: after the addition constitutes an overflow if it
is equal to 1.
• The value of E: is transferred into the add-overflow flip-flop
AVF.
• The two magnitudes are subtracted if the signs are different
for an add operation or identical for a subtract operation.
• The magnitudes are subtracted by adding A to the 2's
complement of B.
• No overflow can occur if the numbers are subtracted so AVF
is cleared to 0.
• A 1 in E indicates that A 􀘹 B and the number in A is the
correct result.
• If this number is zero, the sign A, must be made positive to
avoid a negative zero.
• A 0 in E: indicates that A < B. For this case it is necessary to
take the 2's complement of the value in A. This operation can
be done with one micro operation
• A ->+ 1 .
Addition and Subtraction with Signed-2's
Complement Data:
2. Multiplication Algorithms
• The process consists of looking at successive
bits of the multiplier, least significant bit
first.
• If the multiplier bit is a 1, the multiplicand is
copied down; otherwise, zeros are copied
down.
• The numbers copied down in successive lines
are shifted one position to the left from the
previous number.
• Finally, the numbers are added and their sum
forms the product.
Hardware Implementation for Signed-Magnitude Data:
• The multiplier is stored in the Q register and its sign in Qs.
• The sequence counter SC is initially set to a number equal to the number of bits in the
multiplier.
• The counter is decremented by 1 after forming each partial product.
• When the content of the counter reaches zero, the product is formed and the process stops.
• Initially, the multiplicand is in register B and the multiplier in Q.
• The sum of A and B forms a partial product which is transferred to the EA register.
• Both partial product and multiplier are shifted to the right.
• This shift will be denoted by the statement shr EAQ to designate the right shift depicted in
Fig. 10-5.
• least significant bit of A is shifted into the most significant position of Q, the bit from E is
shifted into the most significant position of A, and 0 is shifted into E.
• After the shift, one bit of the partial product is shifted into Q, pushing the multiplier bits one
position to the right.
• In this manner, the rightmost flip-flop in register Q, designated by Qn, will hold the bit of the
multiplier, which must be inspected next.
Hardware Algorithm
Booth Multiplication Algorithm
Booth multiplication algorithm gives a
procedure for multiplying binary integers in
signed-2's complement representation.
• It operates on the fact that strings of 0's in the
multiplier require no addition but just shifting,
and a string of 1's in the multiplier from bit
weight 2k to weight 2m can be treated as 2k + 1-
2 m.
• For example, the binary number 001110 (+14)
has a string of 1's from 23to 21(k = 3, m = 1).
• The number can be represented as 2 k + l - 2m =
24 - 21 = 16 - 2 = 14.
• Therefore, the multiplication x 14, where M is
the multiplicand and 14 the multiplier, can be
done as M x 24 - M X 21
• Thus the product can be obtained by shifting
the binary multiplicand M four times to the left
and subtracting M shifted left once.
• Booth algorithm requires examination of the multiplier bits
and shifting of the partial product.
• Prior to the shifting, the multiplicand may be added to the
partial product, subtracted from the partial product, or
left unchanged according to the following rules:
• 1.The multiplicand is subtracted from the partial product
upon encountering the first least significant 1 in a string of
1's in the multiplier.
• 2. The multiplicand is added to the partial product upon
encountering the first 0 (provided that there was a previous
1) in a string of 0's in the multiplier.
• 3. The partial product does not change when the
multiplier bit is identical to the previous multiplier bit.
• The algorithm works for positive or negative
multipliers in 2's complement representation.
• This is because a negative multiplier ends with
a string of 1's and the last operation will be a
subtraction of the appropriate weight.
• For example, a multiplier equal to - 14 is
represented in 2's complement as 110010 and
is treated as - 24 + 22 - 21 = -14.
• we rename registers A, B, and Q, as AC, BR, and
QR, respectively.
• Q, designates the least significant bit of the
multiplier in register QR .
• An extra flip-flop Q,., is appended to QR to
facilitate a double bit inspection of the multiplier.
• The flowchart for Booth algorithm is shown in
Fig. 10-8. AC and the appended bit QN+1 are
initially cleared to 0 and the sequence counter SC
is set to a number n equal to the number of bits in
the multiplier.
• The two bits of the multiplier in QN, and QN+1 are inspected.
• If the two bits are equal to 1 0, it means that the first 1 in a string of 1' s has
been encountered.
• This requires a subtraction of the multiplicand from the partial product in AC.
• If the two bits are equal to 01, it means that the first 0 in a string of 0' s has been
encountered.
• This requires the addition of the multiplicand to the partial product in AC .
• When the two bits are equal, the partial product does not change.
• An overflow cannot occur because the addition and subtraction of the
multiplicand follow each other.
• As a consequence, the two numbers that are added always have opposite signs,
a condition that excludes an overflow.
• The next step is to shift right the partial product and the multiplier (including bit
Q,.1).
• This is an arithmetic shift right (ashr) operation which shifts AC and QR to the
right and leaves the sign bit in AC unchanged (see Sec. 4-6).
• The sequence counter is decremented and the computational loop is repeated n
times.
Array Multiplier
• Checking the bits of the multiplier one at a time and
forming partial products is a sequential operation that
requires a sequence of add and shift microoperations.
• The multiplication of two binary numbers can be
done with one microoperation by at once.
• This is a fast way of multiplying two numbers since
all it takes is the time for the signals to propagate
through the gates that form the multiplication array.
• However, an array multiplier requires a large number
of gates, and for this reason it was not economical
until the development of integrated circuits.
Half Adder-
• Half Adder is used for the purpose of adding
two single bit numbers.
• Half adders have no scope of adding the carry
bit resulting from the addition of previous bits.
• To overcome this drawback, full adder comes
into play.
Full Adder-
• Full Adder is a combinational logic circuit.
• It is used for the purpose of adding two single
bit numbers with a carry.
• Thus, full adder has the ability to perform the
addition of three bits.
• Full adder contains 3 inputs and 2 outputs
(sum and carry) as shown-
3.Division Algorithms
• Binary division is simpler than decimal division be cause the quotient digits are either
0 or 1 and there is no need to estimate how many times the dividend or partial
remainder fits into the divisor.
• The divisor B consists of five bits and the dividend A, of ten bits.
• The five most significant bits of the dividend are compared with the divisor.
• Since the 5-bit number is smaller than B, we try again by taking the six most
significant bits of A and compare this number with B.
• The 6-bit number is greater than B, so we place a 1 for the quotient bit in the sixth
position above the dividend.
• The divisor is then shifted once to the right and subtracted from the dividend.
• The difference is called a partial remainder because the division could have stopped
here to obtain a quotient of 1 and a remainder equal to the partial remainder.
• The process is continued by comparing a partial remainder with the divisor.
• If the partial remainder is greater than or equal to the divisor, the quotient bit is equal
to 1.
• The divisor is then shifted right and subtracted from the partial remainder. If the partial
remainder is smaller than the divisor, the quotient bit is 0 and no subtraction is needed.
• The divisor is shifted once to the right in any case. Note that the result gives both a
quotient and a remainder.
Hardware Implementation for Signed-Magnitude Data:
• When the division is implemented in a digital computer, it is
convenient to change the process slightly.
• Instead of shifting the divisor to the right, the dividedly, or partial
remainder, is shifted to the left, thus leaving the two numbers in the
required relative position.
• Subtraction may be achieved by adding A to the 2's complement of B.
• The information about the relative magnitudes is then available from
the end-carry.
• The hardware for implementing the division operation is identical to
that required for multiplication and consists of the components shown
in Fig. 10-5.
• Register EAQ is now shifted to the left with 0 inserted into Q, and the
previous value of E lost.
• The numerical example is repeated in Fig. 10-12 to clarify the proposed
division process.
The hardware divide algorithm
• The dividend is in A and Q and the divisor in B.
The sign of the result is transferred into Q, to be
part of the quotient.
• A constant is set into the sequence counter SC to
specify the number of bits in the quotient.
• As in multiplication, we assume that operands are
transferred to registers from a memory unit that has
words of n bits.
• Since an operand must be stored with its sign, one
bit of the word will be occupied by the sign and the
magnitude will consist of n -1 bits.
• A divide-overflow condition is tested by subtracting the divisor in B from half of
the bits of the dividend stored in A.
• If A > B, the divide-overflow flip-flop DVF is set and the operation is terminated
prematurely.
• If A < B, no divide overflow occurs so the value of the dividend is restored by
adding B to A.
• The division of the magnitudes starts by shifting the dividend in AQ to the left with
the high-order bit shifted into E.
• If the bit shifted into E is 1, we know that EA > B because EA consists of a 1
followed by n -1 bits while B consists of only n -1 bits.
• In this case, B must be subtracted from EA and 1 inserted into Q, for the quotient
bit. Since register A is missing the high-order bit of the dividend (which is in E), its
value is EA - 2"-1
• Adding to this value the 2' s complement of B results in
(EA - 2"-1 ) + (2"-1 - B) = EA - B
• The carry from this addition is not transferred to E
if we want E to remain a l.
• If the shift-left operation inserts a 0 into E, the
divisor is subtracted by adding its 2's complement
value and the carry is transferred into E.
• If E = 1, it signifies that A ;, B; therefore, Q, is set
to 1.
• If E = 0, it signifies that A < B and the original
number is restored by adding B to A. In the latter
case we leave a 0 in Q, (0 was inserted during the
shift).
4.Floating-Point Arithmetic
Operations
• A floating point number in computer
registers consists of two parts: a mantissa m
and an exponent e.
• The two parts represent a number obtained
from multiplying m times a radix r raised to
the value of e; thus
• The mantissa may be a fraction or an integer.
• The location of the radix point and the value of
the radix r are assumed and are not included in
the registers.
• For example, assume a fraction representation
and a radix 10.
• The decimal number 537.25 is represented in a
register with m = 53725 and e = 3 and is
• interpreted to represent the floating-point
number
.53725 X 103
• A floating-point number is normalized if the
most significant digit o f the mantissa is
nonzero.
• In this way the mantissa contains the
maximum possible number of significant
digits.
• A zero cannot be normalized because it does
not have a nonzero digit.
• It is represented in floating-point by all 0' s in
the mantissa and exponent.
• Floating-point representation increases the range of
numbers that can be accommodated in a given register.
Consider a computer with 48-bit words.
• Since one bit must be reserved for the sign, the range of
fixed-point integer numbers will be ± (247 - 1), which
is approximately ± 1014
• The 48 bits can be used to represent a floating-point
number with 36 bits for the mantissa and 12 bits for the
exponent.
• Assuming fraction representation for the mantissa and
taking the two sign bits into consideration, the range of
numbers that can be accommodated is
• ±(1 - 2-35) X 22047
• This number is derived from a fraction that
contains 35 1's, an exponent of 11 bits (excluding
its sign), and the fact that 211 - 1 = 2047.
• The largest number that can be accommodated is
approximately 10615, which is a very large
number.
• The mantissa can accommodate 35 bits
(excluding the sign) and if considered as an
integer it can store a number as large as (235 - 1).
• This is approximately equal to 1010, which is
equivalent to a decimal number of 10 digits.
• Computers with shorter word lengths use two
or more words to represent a floating-point
number.
• An 8-bit microcomputer may use four words
to represent one floating-point number.
• One word of 8 bits is reserved for the
exponent and the 24 bits of the other three
words are used for the mantissa.
• Arithmetic operations with floating-point numbers are more
complicated than with fixed-point numbers and their
execution takes longer and requires more complex hardware.
• Adding or subtracting two numbers requires first an
alignment of the radix point since the exponent parts must be
made equal before adding or subtracting the mantissas.
• The alignment is done by shifting one mantissa while its
exponent is adjusted until it is equal to the other exponent.
• Consider the sum of the following floating-point numbers:
• .5372400 X 102
• + .158oooo x 10-1
• It is necessary that the two exponents be equal before the
mantissas can be added.
• We can either shift the first number three positions to the
left, or shift the second number three positions to the right.
• When the mantissas are stored in registers, shifting to the
left causes a loss of most significant digits.
• Shifting to the right causes a loss of least significant
digits.
• The second method is preferable because it only reduces
the accuracy, while the first method may cause an error.
• The usual alignment procedure is to shift the mantissa that
has the smaller exponent to the right by a number of places
equal to the difference between the exponents.
• After this is done, the mantissas can be added:
• . 5372400 X 102
• + . 0001580 X 102
• .5373980 X 102
• When two normalized mantissas are added, the sum may
contain an overflow digit.
• An overflow can be corrected easily by shifting the sum
once to the right and incrementing the exponent.
• When two numbers are subtracted, the result may contain
most significant zeros as shown in the following example:
• .56780 X 105
• - .56430 X 105
• .00350 X 105
• A floating-point number that has a 0 in the most significant position
of the
• mantissa is said to have an underflow.
• To normalize a number that contains an underflow, it is necessary to
shift the mantissa to the left and decrement the b exponent until a
nonzero digit appears in the first position.
• In the example above, it is necessary to shift left twice to
obtain .35000 X 103.
• In most computers, a normalization procedure is performed after each
operation to ensure that all results are in a normalized form.
• Floating-point multiplication and division do not require an alignment
of the mantissas.
• The product can be formed by multiplying the two mantissas and
adding the exponents.
• Division is accomplished by dividing the mantissas and subtracting
the exponents.
Register Configuration:
• The register configuration for floating-point operations is
quite similar to the layout for fixed-point operations.
• As a general rule, the same registers and adder used for
fixed-point arithmetic are used for processing the
mantissas.
• The difference lies in the way the exponents are handled.
• There are three registers, BR, AC , and QR .
• Each register is subdivided into two parts.
• The mantissa part has the same uppercase letter
symbols as in fixed-point representation.
• The exponent part uses the corresponding lower case
letter symbol.
Addition
• During addition or subtraction, the two
floating-point operands are in AC and BR .
• The sum or difference is formed in the AC .
The algorithm can be divided into four
consecutive parts:
• 1. Check for zeros.
• 2. Align the mantissas.
• 3. Add or subtract the mantissas.
• 4. Normalize the result. and Subtraction:
• A floating-point number that is zero cannot be
normalized.
• If this number is used during the computation, the
result may also be zero. Instead of checking for zeros
during the normalization process we check for zeros at
the beginning and terminate the process if necessary.
• The alignment of the mantissas must be carried out
prior to their operation.
• After the mantissas are added or subtracted, the result
may be normalized.
• The normalization procedure ensures that the result is
normalized prior to its transfer to memory.
Multiplication:
• The multiplication of two floating-point numbers requires that we
multiply the mantissas and add the exponents.
• No comparison of exponents or alignment of mantissas is necessary.
• The multiplication of the mantissas is performed in the same way as
in fixed-point to provide a double-precision product.
• The double-precision answer is used in fixed-point numbers to
increase the accuracy of the product.
• In floating-point, the range of a single-precision mantissa combined
with the exponent is usually accurate enough so that only single
precision
• numbers are maintained. Thus the half most significant bits of the
• mantissa product and the exponent will be taken together to form a
single precision floating-point product.
• The multiplication algorithm can be subdivided into four parts:
• 1. Check for zeros.
• 2. Add the exponents.
• 3. Multiply the mantissas.
• 4. Normalize the product.
• Steps 2 and 3 can b e done simultaneously if separate
adders are available for the mantissas and exponents.
• The two operands are checked to determine if they
contain a zero.
• If either operand is equal to zero, the product in the
AC is set to zero and the operation is terminated.
• If neither of the operands is equal to zero, the process
continues with the exponent addition.
Division:
• Floating-point division requires that the exponents be subtracted and the
• mantissas divided.
• The mantissa division is done as in fixed-point except that
• the dividend has a single-precision mantissa that is placed in the AC .
Remember
• that the mantissa dividend is a fraction and not an integer. For integer
• representation, a single-precision dividend must be placed in register Q and
• register A must be cleared. The zeros in A are to the left of the binary point
• and have no signllicance. In fraction representation, a single-precision
dividend
• is placed in register A and register Q is cleared. The zeros in Q are to the
• right of the binary point and have no signllicance.
• The check for divide-overflow is the same as in
Decimal Arithmetic Unit
• Electronic calculators invariably use an internal
decimal arithmetic unit since inputs and outputs are
frequent.
• There does not seem to be a reason for converting the
keyboard input numbers to binary and again converting
the displayed results to decimal, since this process
requires special circuits and also takes a longer time to
execute.
• Many computers have hardware for arithmetic
calculations with both binary and decimal data.
• Users can specify by programmed instructions whether
they want the computer to perform calculations with
binary or decimal data.
BCD Adder:
• Consider the arithmetic addition of two decimal digits in BCD, together with a
possible carry from a previous stage.
• Since each input digit does not exceed 9, the output sum cannot be greater than 9 + 9
+ 1 = 19, the 1 in the sum being an input-carry.
• Suppose that we apply two BCD digits to a 4-bit binary adder.
• The adder will form the sum in binary and produce a result that may range from 0 to
19.
• These binary numbers are listed in Table 10-4 and are labeled by symbols K, Z 8, z4,
Z2, and Z1.
• K is the carry and the subscripts under the letter Z represent the weights 8, 4, 2, and
1 that can be assigned to the four bits in the BCD code.
• The first column in the table lists the binary sums as they appear in the outputs of a 4-
bit binary adder.
• The output sum of two decimal numbers must be represented in BCD and should
appear in the form listed in the second column of the table.
• The problem is to find a simple rule by which the binary number in the first column
can be converted to the correct BCD digit representation of the number in the
second column.
BCD Subtraction:
• A straight subtraction of two decimal numbers will require a
subtract or circuit that will be some what different from a
BCD adder.
• It is more economical to perform the subtraction by taking the
9's or 10's complement of the subtrahend and adding it to the
minuend.
• Since the BCD is not a self-complementing code, the 9' s
complement cannot be obtained by complementing each bit in
the code.
• It must be formed by a circuit that subtracts each BCD digit
from 9.
• The 9's complement of a decimal digit represented in BCD may be obtained by
complementing the bits in the coded representation of the digit provided a correction
is included.
• There are two possible correction methods.
• In the first method, binary 1010 (decimal 10) is added to each complemented digit
and the carry discarded after each addition.
• In the second method, binary 0110 (decimal 6) is added before the digit is
complemented.
• As a numerical illustration, the 9's complement of BCD 0111 (decimal 7) is
computed by first complementing each bit to obtain 1000.
• Adding binary 1010 and discarding the carry, we obtain 0010 (decimal 2). By the
second method, we add 0110 to 0111 to obtain 1101.
• Complementing each bit, we obtain the required result of 0010.
• Complementing each bit of a 4-bit binary number N is identical to the subtraction of
the number from 1111 (decimal 15).
• Adding the binary equivalent of decimal 10 gives 15 - N + 10 = 9 - N + 16.
• But 16 signifies the carry that is discarded, so the result is 9 - N as required.
• Adding the binary equivalent of decimal 6 and then complementing gives 15 - (N +
6) = 9 - N as required.
Decimal Arithmetic Operations
• Registers A and B have four more bits designated by A, and
B, that provide an extension of one more digit to the
registers.
• The BCD arithmetic unit adds the five digits in parallel and
places the sum in the five-digit A register.
• The end-carry goes to flip-flop E.
• The purpose of digit A, is to accommodate an overflow
while adding the multiplicand to the partial product during
multiplication.
• The purpose of digit B, is to form the 9's complement of the
divisor when subtracted from the partial remainder during
the division operation.
• The least significant digit in register Q is denoted by QL .
• This digit can be incremented or decremented.
• A decimal operand coming from memory consists of 17 bits. One bit (the sign) is transferred
to B, and the magnitude of the operand is placed in the lower 16 bits of B .
• Both B, and A, are cleared initially.
• The result of the operation is also 17 bits long and does not use the A, part of the A register.
• The decimal multiplication algorithm is shown in Fig. 10-22.
• Initially, the entire A register and B, are cleared and the sequence counter SC is set to a
number k equal to the number of digits in the multiplier.
• The low-order digit of the multiplier in Q, is checked. If it is not equal to 0, the multiplicand in
B is added to the partial product in A once and QL is decremented.
• QL is checked again and the process is repeated until it is equal to 0.
• In this way, the multiplicand in B is added to the partial product a number of times equal to
• the multiplier digit. Any temporary overflow digit will reside in A, and can
• range in value from 0 to 9.
• Next, the partial product and the multiplier are shifted once to the right.
• This places zero in A, and transfers the next multiplier quotient into QL.
• The process is then repeated k times to form a double-length product in AQ .
Division:
• Decimal division is similar to binary division except of
course that the quotient digits may have any of the 10
values from 0 to 9.
• In the restoring division method, the divisor is
subtracted from the dividend or partial remainder as
many times as necessary until a negative remainder
results.
• The correct remainder is then restored by adding the
divisor.
• The digit in the quotient reflects the number of
subtractions up to but excluding the one that caused the
negative difference.
• The decimal division algorithm is shown in Fig. 10-23. It is similar to the
algorithm with binary data except for the way the quotient bits are formed.
• The dividend (or partial remainder) is shifted to the left, with its most
significant digit placed in A, . The divisor is then subtracted by adding its 10'
s complement value.
• Since B, is initially cleared, its complement value is 9 as required.
• The carry in E determines the relative magnitude of A and B. If E = 0, it
signifies that A < B. In this case the divisor is added to restore the partial
remainder and QL stays at 0 (inserted there during the shift). If E = 1, it
signifies that A ;,: B.
• The quotient digit in QL is incremented once and the divisor subtracted
again.
• This process is repeated until the subtraction results in a negative difference
which is recognized by E being 0.
• When this occurs, the quotient digit is not incremented but the divisor is
added to restore the positive remainder.
• In this way, the quotient digit is made equal to the number of times that the
partial remainder "goes" into the divisor.