University Institute of Engineering

Department of Computer Science & Engineering

COMPUTER ORGANIZATION & ARCHITECTURE

(23CST-204/23ITT-204)

ER. SHIKHA ATWAL

E11186

ASSISTANT PROFESSOR

BE-CSE
 INSTRUCTION SET CLASSIFICATION

The instruction set of any processor broadly fits into the categories as in figure
below along with examples. The first five categories are mandatory while the
next four are generally
available in advanced or new generation processors. The Instruction set is part of
the Instruction Set Architecture (ISA). Therefore, the Data path, the Registers,
Memory Interface and the Instruction set, altogether ensure the design of the
CPU and its best utilization. The number of instructions for a processor may
range from less than 100 to few hundreds plus. It is noteworthy, that a large
number of instructions does not imply that the processor is powerful. More often,
to provide downward compatibility within the processor family variants of each
instruction adds up to the list, making the set larger.
Generic Classification of Instruction Set
Generic types of instructions are already discussed in previous chapters. Let us
understand others and previous ones in brief.

For easy understanding, the examples are written in the mnemonic code. R
refers to register in CPU, any name refers to the variable.
First part is the instruction mnemonic.
The example instructions do not pertain to any particular CPU.

Data Movement Instructions: These support movement of data between

registers, registers to memory, memory to register. Few CPU support
memory to memory movement of data too. Data movement instructions
are named as either “Move” or Load/Store” instructions. This category
is most frequently used by CPU while executing program code.
For example:

Move R1, Total

Move Total, R1
Load R1, Total
Store R1, Total

Arithmetic and Logical Instructions: This category of instructions carry out

calculations. The minimum in this category is ADD, SUB, AND, OR, XOR,
SHIFT. Multiply and Divide can always be emulated using successive addition or
subtraction. This was the case in very early systems. However, MULTIPLY and
DIV are part of the instruction set as hardware execution is more efficient
than emulation. Few CPUs have CMP (Compare) instruction.
The logical instructions are required to implement the condition checking of
"For Loops, While Loops, IF, etc..".

At the end of execution of arithmetic and logical instructions, depending

on the result in Accumulator, Condition Codes (Zero, Sign, Overflow, carry –
ZSOC) are set, implying the outcome of the instruction execution. Generally,
these flags are useful in controlling the flow of the program. For example:

ADD R1, TOTAL

ADD R1, R2, R3
XOR R4, TOTAL
MUL R4, MARKS
Transfer or Control Instructions: This category of instructions facilitate change in
program flow described by the control structures in the high-level language.
BRANCH or JMP instructions along with Condition Code flags achieve the
requirement. Subroutine CALLS, RETURNS are categorized here.
For example:

JMP LABEL1 ;Jump

JNZ LABEL2 ;Jump on not zero
BZ LABEL2 ;Branch on Zero
BNE LABEL3 ;Branch on not Equal
Input/Output Instructions: There are two ways of doing Input/Output operations.
Intel family uses In and Out Instructions on the I/O registers for communication or
data transfer with I/O devices. These I/O registers are numbered as Ports.
Motorola family uses Data movement instructions assigning memory addresses
to I/O registers. The former is called I/O mapped I/O whereas the latter is called
Memory-mapped I/O.

For example:
IN Port#232
OUT Port#234
Move R1, #FFEE
Miscellaneous Instructions: NOP (No Operation) is a famous dummy instruction
but a very useful one in this category. Some of the CPUs allow user-defined
interrupt. These interrupts can be activated using Instructions. HALT is another very
important instruction which brings the system to halt when "Shutdown". System
Control is either grouped here or as Control Instructions.

For example:

HALT
NOP
INT
Floating Point Instructions: We had seen in the previous chapter that specialised
hardware is required for efficient Floating-point operations. This hardware
works independently of the CPU. Floating-Point Arithmetic instructions with
unique opcode are helpful.

FLD FP Load
FST FP Store
FADD FP ADD
FSUB FP Subtract
FMUL FP Multiply

Binary Coded Decimal Instructions: Decimal Number system hardware speeds up

decimal calculations. In the absence of this hardware, every time conversion to
binary and reverse conversion to decimal is required. Similar to floating
arithmetic instructions specialized decimal hardware is available.
Vector Instructions: This group is specific to display. Graphic operations like
zoom, resize, flip etc require heavy calculations on Vector basis. Matrices
operations utilize vector instructions.

Emulated Instructions: User-defined opcode and operation fall into this category.
Very few CPU support this type.
CPU architecture design radically differs based on the size of the Instruction set.
Accordingly, there are two categories namely Reduced Instruction Set
Computer (RISC) and Complex Instruction Set Computer (CISC).

As the name implies, RISC has fewer instructions in the set and CISC has a large
number of instructions. No matter, both are equally functionally complete. MIPS,
ALPHA, PA-RISC, Intel i860, Motorola 88000, ARM are all examples of RISC
CPU. Intel X86 series, Motorola 68K series, VAX are all examples of CISC CPU.
Frequently we will be referring to RISC and CISC. The trade-off is between the
size of the program code and the simplicity in decoding the instructions by the
hardware.
INSTRUCTION SET FORMATS

The Instruction Set Format defines how an instruction is structured in a

computer system, specifying the arrangement of various fields that encode
information for the processor to execute. The format typically includes fields
like the opcode, operands, and sometimes additional metadata.

Basic Fields in an Instruction Format

1. Opcode (Operation Code):

oSpecifies the operation to be performed (e.g., ADD, SUB, MOV).
oDetermines the type of operation (arithmetic, logical, data transfer, etc.).
2. Operand(s):
oSpecifies the data to be used in the operation. This could be:
▪Registers: Data stored in processor registers.
▪Memory Addresses: Direct or indirect locations in memory.
▪Constants/Immediate Values: Fixed values provided in the instruction.
3. Addressing Mode:
oDefines how the operand is interpreted (immediate, direct, indirect, indexed,
etc.).
4. Instruction Length:
oSpecifies the number of bits used to represent the entire instruction (e.g., 16-
bit, 32-bit, 64-bit).
Key Considerations in Instruction Formats

1.Length of the Instruction:

oShorter instructions save memory but may limit functionality.
oLonger instructions can encode more information.
2.Number of Operands:
oAffects the instruction size and flexibility.
oZero to three operands are common.
3.Addressing Modes:
oDetermines the way operands are accessed, influencing instruction
complexity.
4.Ease of Decoding:
oFixed-length formats simplify decoding but may waste memory.
oVariable-length formats save memory but complicate decoding.
Types of Instruction Formats

Encoding of Instructions is called Instruction Format. There are two generic ways
to encode instructions.

1. Fixed length Instruction Format: RISC uses fixed-length encoding in

which each Instruction occupies the same amount of space. The length of the
instruction is fixed irrespective of the opcode. It simplifies instruction decoding.

An example of Fixed Length Instruction format – MIPS series

 MIPS series is a RISC processor. It simply has 3 variants of formats but all have
the same word length. Also, it is observed that registers are used than the
memory in referencing operands.

2. Variable Length Instruction Format: CISC uses variable-length encoding in

which each instruction occupies only the space required by it to convey the
operands. No redundant use of memory space. It allows compact representation of
instructions but complicates decoding.
 This is a supportive figure to understand
the characteristics of a variable-length
format. As you see, there 8 ways in
which the instruction is encoded varying
from 2 bytes length to 8 bytes length. It
is observed that the length differs
depending upon the way the operand
address is conveyed.

An example of Variable Length Instruction format with Motorola M6800

CISC CPU
Common Instruction Formats
In terms of specifically related to instructions, there are three other types of
Instruction set formats.

1.Three-Address Format

 Used when three operands are specified (source1, source2, destination).

 Example:

ADD R1, R2, R3 ;R1 = R2 + R3

Format: Opcode | Source1 (R2) | Source2 (R3) | Destination (R1)

2. Two-Address Format

 Used when two operands are specified. The result is stored in one of the source
operands.
 Example:

ADD R1, R2 ;R1 = R1 + R2

Format: Opcode | Source/Destination (R1) | Source (R2)

3. One-Address Format

 One operand is implied (usually the accumulator).

 Example:

ADD A ;AC = AC + A

Format: Opcode | Address (A)

4. Zero-Address Format (Stack-Based)

 Operands are implied to be on the top of the stack.

 Example:

ADD ;TOS = (TOS - 1) + TOS

PUSH
POP

Format: Opcode
Exercise:

Write the below expression in all address formats of instructions.

X = (A+B)*(C+D)
X = (A+B)*(C+D) in Three Address Format

ADD R1, A, B ;R1=M[A]+M[B]

ADD R2, C, D ;R2=M[C]+M[D]
MUL X,R1, R2 ;M[X]=R1*R2

X = (A+B)*(C+D) in Two Address Format

MOV R1, A ;R1=M[A]

ADD R1, B ;R1=R1+M[B]
MOV R2, C ;R2=M[C]
ADD R2, D ;R2=R2+M[D]
MUL R1, R2 ;R1=R1*R2
MOV X, R1 ;M[X]=R1
X = (A+B)*(C+D) in One Address Format

LOAD A ;AC=M[A]
ADD B ;AC=AC+M[B]
STORE T ;M[T]=AC
LOAD C ;AC=M[C]
ADD D ;AC=AC+M[D]
MUL T ;AC=AC*M[T]
STORE X ;M[X]=AC
X = (A+B)*(C+D) in Zero Address Format

PUSH A ;TOP=A
PUSH B ;TOP=B
ADD
PUSH C ;TOP=C
PUSH D ;TOP=D
ADD ;TOP=C+D
MUL ;TOP=(C+D)*(A+B)
POP X ;M[X]=TOP
References Reference Books:
 J.P. Hayes, “Computer Architecture and Organization”,
Third Edition.
 Mano, M., “Computer System Architecture”, Third
Edition, Prentice Hall.
 Stallings, W., “Computer Organization and Architecture”, Eighth Edition,
Pearson Education.
Text Books:
 Carpinelli J.D,” Computer systems organization &Architecture”, Fourth
Edition, Addison Wesley.
 Patterson and Hennessy, “Computer Architecture” , Fifth Edition Morgaon
Kauffman.
Reference Website
 Instruction Set Architecture : Instructions and Formats | Computer
Architecture (witscad.com)