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Programmable Logic Devices

The document discusses Programmable Logic Devices (PLDs), which are electronic components for building reconfigurable digital circuits, and outlines their types: PROM, PAL, and PLA. It explains the programming process for these devices, detailing how they can implement Boolean functions. Additionally, it covers advanced PLDs like CPLDs and FPGAs, and addresses race conditions in asynchronous circuits.

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7 views39 pages

Programmable Logic Devices

The document discusses Programmable Logic Devices (PLDs), which are electronic components for building reconfigurable digital circuits, and outlines their types: PROM, PAL, and PLA. It explains the programming process for these devices, detailing how they can implement Boolean functions. Additionally, it covers advanced PLDs like CPLDs and FPGAs, and addresses race conditions in asynchronous circuits.

Uploaded by

baghyashreesekar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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UNIT IV

PROGRAMMABLE LOGIC DEVICES


Programmable Logic Devices

• A Programmable Logic Device


(PLD) is an electronic component
used to build reconfigurable
digital circuits.
• Unlike digital logic constructed using
discrete logic gates with fixed
functions, a PLD has an undefined
function at the time of
manufacture.
What is inside PLD?
• They contain an array of AND gates &
another array of OR gates.
Types of Programmable Logic Devices
(PLD)

There are three kinds of PLDs based on the


type of arrays, which has programmable
feature

1. Programmable Read Only Memory


(PROM)
2. Programmable Array Logic (PAL)
3. Programmable Logic Array (PLA)
What is programming in
PLD?
• The process of entering the information
into these devices is known
as programming.
• Basically, users can program these
devices or ICs electrically in order to
implement the Boolean functions based
on the requirement.
• Here, the term programming refers to
hardware programming but not software
programming.
Programmable Read Only Memory
(PROM)

• If the ROM has programmable feature, then it


is called as Programmable ROM
• The user has the flexibility to program the
binary information electrically once by using
PROM programmer.
PROM contd…
• PROM is a programmable logic
device that has fixed AND array &
Programmable OR array. The block
diagram of PROM is shown in the
following figure.
How PROM is programmed?

• Here, the inputs of AND gates are not of


programmable type. So, we have to generate
2n product terms by using 2n AND gates having
n inputs each. We can implement these product
terms by using nx2n decoder. So, this decoder
generates ‘n’ min terms.
• Here, the inputs of OR gates are
programmable. That means, we can program
any number of required product terms, since all
the outputs of AND gates are applied as inputs to
each OR gate. Therefore, the outputs of PROM will
be in the form of sum of min terms.
Design using PROM : Example 1
Here, 3 to 8 decoder generates eight min terms.
The two programmable OR gates have the access of all these min
terms. But, only the required min terms are programmed in order to
produce the respective Boolean functions by each OR gate.
The symbol ‘X’ is used for programmable connections.
Design using PROM : Example 2

• Design a combinational circuit which accepts


three bit binary number and outputs a binary
number equal to the square of the input number
using PROM.
3:8 Decoder
Implementation using PROM

• Size of PROM : number of inputs x Number of outputs

Input Output Output


A B C Decimal Y1 Y2 Y3 Y4 Y5 Y6
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 1
0 1 0 4 0 0 0 1 0 0
0 1 1 9 0 0 1 0 0 1
1 0 0 16 0 1 0 0 0 0
1 0 1 25 0 1 1 0 0 1

1 1 0 36 1 0 0 1 0 0
1 1 1 49 1 1 0 0 0 1

• Size of PROM : 3 x 6
Implementation using PROM
Programmable Array Logic
(PAL)
• PAL is a programmable logic device
that has Programmable AND array &
fixed OR array.
• The advantage of PAL is that we can
generate only the required product
terms of Boolean function instead of
generating all the min terms by using
programmable AND gates
PAL – contd…

Here, the inputs of AND gates are programmable. That means each
AND gate has both normal and complemented inputs of variables. So,
based on the requirement, we can program any of those inputs. So,
we can generate only the required product terms by using these
AND gates.

Here, the inputs of OR gates are not of programmable type. So, the
number of inputs to each OR gate will be of fixed type. Hence, apply
those required product terms to each OR gate as inputs. Therefore,
the outputs of PAL will be in the form of sum of products form.
Programmable Array Logic
(PLA)
• PLA is a programmable logic device that has
both Programmable AND array &
Programmable OR array.
• Hence, it is the most flexible PLD.
PLA-contd…
Example Problem in PLA
Implementation using PLA
Example Problem in PAL
Complex Programmable Logic Devices
(CPLDs)
• A CPLD contains a bunch of PLD blocks whose
inputs and outputs are connected together by
a global interconnection matrix.
• Thus a CPLD has two levels of
programmability:
• each PLD block can be programmed, and then
the interconnections between the PLDs can be
programmed.
Block Diagram of CPLD
Field Programmable Gate Arrays (FPGAs)

• The FPGA consists of 3 main structures:


1. Programmable logic structure,
2. Programmable routing structure, and
3. Programmable Input/Output (I/O)
Programmable Logic Structure
Programmable Routing Structure
Programmable I/Os
RACE CONDITION
• A race condition is said to exist in an
asynchronous sequential circuit when two or
more binary state variables change value in
response to a change in an input variable.
• When unequal delays are encountered a race
condition may cause the stale variables to
change in an unpredictable manner.
Non critical races

If the final stable state that the circuit reaches does not depend on the order
in which the state variables change, the race is called a noncritical race.
Critical Races

If it is possible to end up in two or more different stable stares, depending on the


order in which the state variables change, then the race is a critical race
Unit III : Race around condition:

• Race Around Condition In JK Flip-flop


For J-K flip-flop, if J=K=1, and if clk=1 for a long
period of time, then Q output will toggle as long as
CLK is high, which makes the output of the flip-flop
unstable or uncertain. This problem is called race
around condition in J-K flip-flop.

This problem (Race Around Condition) can be avoided


by ensuring that the clock input is at logic “1” only
for a very short time.
Master Slave JK Flip flop

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