Fundamental Concepts

 Maximum size of the Main Memory

 byte-addressable
 CPU-Main Memory Connection

Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
 Measures for the speed of a memory:
 memory access time.
 memory cycle time.
 An important design issue is to
provide a computer system with as
large and fast a memory as possible,
within a given cost target.
 Several techniques to increase the
effective size and speed of the
memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).
Semiconductor RAM memories
 Each memory cell can hold one bit of information.
 Memory cells are organized in the form of an array.
 One row is one memory word.
 All cells of a row are connected to a common line,
known as the “word line”.
 Word line is connected to the address decoder.
 Sense/write circuits are connected to the data
input/output lines of the memory chip.
 7 7 1 1 0 0
W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
decoder • • • • • • cells
A2 • • • • • •
• • • • • •
A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R /W

circuit circuit circuit
CS

Data input /output lines: b7 b1 b0

 The previous figure is an example of a very small memory circuit
consisting of 16 words of 8 bits each. This is referred to as a 16 × 8
organization. The data input and the data output of each
Sense/Write circuit are connected to a single bidirectional data line
that can be connected to the data lines of a computer. Two control
lines, R/W and CS, are provided. The R/W Read/Write) input
specifies the required operation, and the CS (Chip Select) input
selects a given chip in a multichip memory system.

 The memory circuit stores 128 bits and requires 14 external

connections for address, data, and control lines. It also needs two
lines for power supply and ground connections. Consider now a
slightly larger memory circuit, one that has 1K (1024) memory cells.
This circuit can be organized as a 128 × 8 memory, requiring a total
of 19 external connections. Alternatively, the same number of cells
can be organized into a 1K×1 format. In this case, a 10-bit address
is needed, but there is only one data line, resulting in 15 external
The required 10-bit address is divided into two groups of 5 bits each to form the row
and column addresses for the cell array. A row address selects a row of 32 cells, all
of which are accessed in parallel. But, only one of these cells is connected to the
external data line, based on the column address.
Read-Only Memories (ROMs)
 SRAM and SDRAM chips are volatile:
 Lose the contents when the power is turned off.
 Many applications need memory devices to retain
contents after the power is turned off.
 For example, computer is turned on, the operating
system must be loaded from the disk into the memory.
 Store instructions which would load the OS from the disk.
 Need to store these instructions so that they will not be
lost after the power is turned off.
 We need to store the instructions into a non-volatile
memory.
 Non-volatile memory is read in the same manner as
volatile memory.
 Separate writing process is needed to place information
in this memory.
 Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
 Read-Only Memory:
 Data are written into a ROM when it is manufactured.
 Programmable Read-Only Memory
(PROM):
 Allow the data to be loaded by a user.
 Process of inserting the data is irreversible.
 Storing information specific to a user in a ROM is expensive.
 Providing programming capability to a user may be better.

 Erasable
Programmable Read-Only
Memory (EPROM):
 Stored data to be erased and new data to be loaded.
 Flexibility, useful during the development phase of digital systems.
 Erasable, reprogrammable ROM.
 Erasure requires exposing the ROM to UV light.
 Electrically Erasable Programmable Read-Only
Memory (EEPROM):
 To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
 Physically removed from the circuit.
 EEPROMs the contents can be stored and erased electrically.
 Flash memory:
 Has similar approach to EEPROM.
 Read the contents of a single cell, but write the
contents of an entire block of cells.
 Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
 Power consumption of flash memory is very low,
making it attractive for use in equipment that is
battery-driven.
 Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
A big challenge in the design of a
computer system is to provide a
sufficiently large memory, with a
reasonable speed at an affordable cost.
 Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a complex
circuit making it impossible to pack a large number of cells onto a
single chip.
 Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive, but
significantly slower than SRAMs.
 Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is still less than
what is necessary.
 Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
 Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing •Relatively small amount of memory that
Increasing Increasing
size speed cost percanbit be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory
Cache Memories
 Processor is much faster than the main
memory.
 As a result, the processor has to spend much of its time waiting while
instructions and data are being fetched from the main memory.
 Major obstacle towards achieving good performance.
 Speed of the main memory cannot be
increased beyond a certain point.
 Cache memory is an architectural
arrangement which makes the main
memory appear faster to the processor
than it really is.
 Cache memory is based on the property
of computer programs known as “locality
of reference”.
 Analysisof programs indicates that
many instructions in localized areas of
a program are executed repeatedly
during some period of time, while the
others are accessed relatively less
frequently.
 These instructions may be the ones in a loop, nested loop or few
procedures calling each other repeatedly.
 This is called “locality of reference”.
 Temporal locality of reference:
 Recently executed instruction is likely to be executed again very
soon.
 Spatial locality of reference:
 Instructions with addresses close to a recently instruction are likely
to be executed soon.
 Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred

from the main memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found
in the cache.
• At any given time, only some blocks in the main memory are held in
the cache. Which blocks in the main memory are in the cache is
determined by a “mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
• Existence of a cache is transparent to
the processor. The processor issues
Read and Write requests in the same
manner.

• If the data is in the cache it is called a

Read or Write HIT.
• If the data is not present in the cache,
then a Read miss or Write MISS
occurs.