VLSI
VLSI
DESIGN
ECT 304
MODULE 1
Introduction
Moore’s law .
ASIC design, Full custom ASICs, Standard cell based ASICs, Gate array based ASICs,
SoCs
FPGA devices
ASIC and FPGA Design flows
Top-Down and Bottom-Up design methodologies.
Logical and Physical design.
Speed power and area considerations in VLSI design
Integrated Circuit (IC)
VLSI, or Very Large Scale Integration, refers to the process of integrating millions or
billions of transistors onto a single semiconductor chip.
This technology is used in microprocessors, memory chips, and advanced AI
processors.
VLSI technology enables the development of powerful yet compact electronic
devices such as smartphones, laptops, and embedded systems.
The advancement of VLSI follows Moore’s Law,
Moore’s Law
“which states that the number of transistors on a chip doubles approximately every
two years. This has led to exponential growth in computing power while reducing
power consumption and cost ’’
ASIC (Application-Specific Integrated Circuit)
ASIC[“a-sick”] is an acronym for Application Integrated Circuit
An Application-Specific Integrated Circuit, or ASIC, is a type of integrated circuit (IC)
designed for a specific application or function rather than for general-purpose use.
Unlike general-purpose processors, which can perform multiple tasks, an ASIC is
optimized for a particular operation, making it more efficient in terms of speed, power
consumption, and size
For instance, an ASIC used in a smartphone camera is specifically designed for image
processing, ensuring fast and high-quality photo capture
Why Do We Need ASICs
General-purpose processors, like CPUs, are designed to handle a variety of tasks, but
they may not be the most efficient for specialized applications. ASICs, on the other
hand, provide:
Pre-designed silicon wafer with a fixed array of unconnected transistors and gates.
Logic functions are implemented by connecting transistors through metal
interconnections.
There are Three types of Gate array based ASIC.
1. Channeled gate arrays
2. channelless gate array
3. structured gate arrays
Channelled Gate Array
Fixed rows of unconnected logic gates with predefined routing channels between
them.
These channels contain reserved spaces for metal interconnections during the
customization stage.
Transistors are not densely packed because space is left for routing.
Channelless gate array
No predefined routing channels; instead, logic gates are placed uniformly across the
chip.
Interconnections are made in the upper metal layers, reducing wasted space.
Utilizes higher transistor density compared to channeled gate arrays.
Structured Gate array
A hybrid approach between gate arrays and standard-cell ASICs.
Contains predefined logic blocks alongside a gate array.
Custom logic is implemented using the gate array, while fixed-function blocks speed up
design.
Advantages Of Gate array Based ASIC
Pre-fabricated wafers – Reduces manufacturing lead time.
Customizable metal layers – Optimizes routing for specific applications.
Cost-effective for moderate production runs.
Faster development than standard cell and full custom ASICs.
Design Flexibility Limited due to pre-defined High flexibility as custom logic cells
transistor arrays. are used.
Design Time Shorter (only metal layers are Shorter (only metal layers are
designed). designed).
Fabrication Time Faster as only metal layers are Longer because logic cells and
processed. interconnections are custom-
designed.
Performance Moderate performance due to fixed Higher performance as logic is
transistor layout. optimized for the application.