Interview process strucure for “ASIC front-end design” role

Topics Typical questions

• Intro
• from hiring manager on the team and company
• from candidate

• Initial Screening
• Background overview: Experience with ASIC design and key projects. • Walk through a challenging ASIC design project you've worked on?
• Familiarity with EDA tools, RTL coding, synthesis, STA, etc. • Which tools have you used for synthesis, verification, and STA?

• What is AMBA?
• Technical Interview • Explain metastability. How do you handle it?
• Design principles: State machines, pipelining, clock domain crossing. • What is your approach to designing a multi-clock domain system?
• MBIST, DFT • Verification concepts: Assertions, functional coverage, debugging techniques.
• Low-power design: UPF/CPF concepts. • Power: dynamic vs. static power, techniques for power optimization
• How does clock gating reduce power
• Low-power design: UPF/CPF concepts.
• Explain the role of level shifter cells in power gating
• Timing violations: Setup/hold time. How do you resolve ?
• What are false paths and how do you handle them?
• Explain multi-cycle paths and their impact on timing.
• What is DFT/MBIST purpose? Difference between LBIST and SCAN?

• Behavioral/Managerial
• Soft skills: • How do you prioritize tasks when multiple deadlines overlap?
• Communication, teamwork. • How do you handle tight project deadlines?
• Approach to challenges. • Describe a situation where you resolved a technical disagreement within a team

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Design, Verilog/SystemVerilog . . .

always @(posedge i_clock)

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Synchronizers
• What is metastability?
• How to check CDC in design?
• How can a single-bit signal be synchronized from a slow clock domain
to a fast clock domain?
• What is dual flop synchronizer?
• What is MTBF (Mean Time Between Failures)?
• How can be bus synchronized from a slow clock domain to fast clock
domain?
• What is bus synchronizer?

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Synchronizers
• How can a single-bit signal be synchronized from a fast clock domain
to a slow clock domain?
• What is toggle synchronizer?
• What is pulse synchronizer ?
• What is Gray encoding ?
• FIFO design step by step.

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What is the purpose of scan flip-flops and scan chains in Design for Testability (DFT).

FF scan_ff

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What ATPG pattern will help to find the defect

1 O
C
0
D

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Find the bug(s) and explain what will be the synthesis result of the code below:

module blking_eg (
module blking_eg ( input wire clk,
input wire clk, input wire rst,
input wire rst, input wire d,
input wire d, output reg q
output reg q );
);
always @(posedge clk or posedge rst) begin
always @(posedge clk) begin if (rst)
if (rst) q = 0;
q = 0; else
else q = d;
q = d; end
end
emdmodule
emdmodule

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Find the bug(s) and explain what will be the synthesis result of the code below:

module basic_block (
input wire en_i, // Enable signal
input wire in_i, // Input signal
inout reg io // Bidirectional port
);

assign io = en_i ? in_i : 'bz;

endmodule // basic_block

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What will be the synthesis result of the code below:
module basic_block (
input clk_i,
input rstn_i,
input enable_i,
input in_i,
output out_o
);

reg out_r;

always @(enable_i or rstn_i) begin

endmodule // basic_block

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FIFO, LIFO

• Explain the operation of a FIFO (First-In-First-Out) queue.

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