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Interrupt Structure and Its Servicing

Gdeh

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10 views13 pages

Interrupt Structure and Its Servicing

Gdeh

Uploaded by

sujalp9223
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Interrupt structure and its servicing

Interrupt is the method of creating a temporary halt during program execution and
allows peripheral devices to access the microprocessor.

The microprocessor responds to that interrupt with an ISR (Interrupt Service


Routine), which is a short program to instruct the microprocessor on how to handle
the interrupt
Condition Produced by Instruction:
8086 responds to the interrupt by performing series of actions:

● It decrements stack pointer by 2 and pushes the flag register on the stack..
● It disables the INTR interrupt input by clearing the interrupt flag in the flag
● It resets the trap flag in the flag register.
● It decrements stack pointer by 2 and pushes the current code segment register
contents on the stack.
● It decrements stack pointer by 2 and pushes the current instruction pointer
contents on the stack.
● It does an indirect far jump at the start of the procedure by loading the CS and
IP values for the start of the interrupt service routine (ISR).

An IRET instruction at the end of the interrupt service procedure returns execution
to the main program.
Interrupt Vector Table 8086
In an Interrupt Structure of 8086 system the first 1 Kbyte of memory from 00000H
to 003FFH is reserved for storing the starting addresses of interrupt service
routines. This block of memory is often called the Interrupt Vector Table in 8086
or the interrupt pointer table.

Each interrupt type is given a number between 0 to 255 and the address of each
interrupt js found by multiplying the type by 4 e.g. for type 11, interrupt address is
11 x 4 = 4410= 0002CH

Only first five types have explicit definitions such as divide by zero and non
maskable interrupt. The next 27 interrupt types, from 5 to 31, are reserved by Intel
for use in future microprocessors. The upper 224 interrupt types, from 32 to 255,
are available for user for hardware or software interrupts.
Types:
Interrupt

Hardware
software

Maskable Non-Maskable
Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.

NMI
When this interrupt is activated, these actions take place −
Completes the current instruction that is in progress.
Pushes the Flag register values on to the stack.
Pushes the CS (code segment) value and IP (instruction pointer) value of the return address
on to the stack.
IP is loaded from the contents of the word location 00008H.
CS is loaded from the contents of the next word location 0000AH.
Interrupt flag and trap flag are reset to 0.
INTR
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then
the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first
‘0’ means INTA informs the external device to get ready and during the second ‘0’ the
microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
First completes the current instruction.
Activates INTA output and receives the interrupt type, say X.
Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.
IP value is loaded from the contents of word location X × 4
CS is loaded from the contents of the next word location.
Interrupt flag and trap flag is reset to 0.
Software Interrupts
Some instructions are inserted at the desired position into the program to create
interrupts. These interrupt instructions can be used to test the working of various
interrupt handlers

INT- Interrupt instruction with type number


It is 2-byte instruction. First byte provides the op-code and the second byte
provides the interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
Flag register value is pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on
to the stack.
IP is loaded from the contents of the word location ‘type number’ × 4
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0
The first five pointers are dedicated interrupt pointers. i.e. –
TYPE 0 interrupt represents division by zero situation.
TYPE 1 interrupt represents single-step execution during the debugging of a program.
TYPE 2 interrupt represents non-maskable NMI interrupt.
TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and interrupts from 32 to Type 255 are available for hardware and
software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH.
Its execution includes the following steps −
Flag register value is pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on
to the stack.
IP is loaded from the contents of the word location 3×4 = 0000CH
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is
CEH
Its execution includes the following steps −
Flag register values are pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on to the
stack.
IP is loaded from the contents of word location 4×4 = 00010H
CS is loaded from the contents of the next word location.
Interrupt flag and Trap flag are reset to 0

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