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Uvm Basics - Uvm TLM

The document provides an overview of Transaction Level Modeling (TLM) within the UVM framework, detailing its methods, communication types, and testbench structure. It covers blocking and non-blocking operations, TLM ports, exports, and the importance of analysis components. Additionally, it introduces TLM 2.0 and emphasizes the necessity of connecting ports to implementations in UVM testbenches.

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Sachin Igoor
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41 views26 pages

Uvm Basics - Uvm TLM

The document provides an overview of Transaction Level Modeling (TLM) within the UVM framework, detailing its methods, communication types, and testbench structure. It covers blocking and non-blocking operations, TLM ports, exports, and the importance of analysis components. Additionally, it introduces TLM 2.0 and emphasizes the necessity of connecting ports to implementations in UVM testbenches.

Uploaded by

Sachin Igoor
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 26

SDG HAC SOC VAL - UVM

Training
UVM TLM

Jonathan Mathews

Intel Confidential
02/07/2025
1
Contents

 Introduction
 What is TLM? Why?
 Usage
 UVM TLM methods
 Communication types
 Blocking and Non-blocking
 TLM Ports, Exports and Imps
 Analysis ports
 Subscribers
 TLM & Analysis FIFO
 TLM 2.0

2 02/07/2025 Intel Confidential


Testbench structure

UVM Testbench

UVM Test
Sequence Sequence

UVM Enviroment

Agent Agent

Sequencer Scoreboard Sequencer

Driver Monitor Monitor Driver

DUT

3 02/07/2025 Intel Confidential


Introduction

• Transaction Level Modeling


• Communication between components(ports)
• Higher level abstraction(transactions/objects)
• Reusable(plug and play)
• Maintainable and ease of implementation
• Connect to external env(SystemC)

4 02/07/2025 Intel Confidential


Introduction

• Communication via
method calls

• Port specifies the API

• Export supplies the


implementation

• Parameterized by the
transaction /object type

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UVM TLM Methods/APIs

• Blocks until it can successfully


complete its operation
• Single Producer to single consumer

• Put(push)
• Pushes an object across the interface
• Doesn’t overwrite an object

• Get(pull)
• Pulls an object across the interface
• Removes the object from the other
side

• Peek
• Similar to get but doesn’t remove the
object

6 02/07/2025 Intel Confidential


UVM TLM Methods – Blocking vs Non-blocking

• Unlike their blocking counterparts,


these do not block in the initiator

• Try_put/can_put
• Returns 1 if it was able to or could
put an object

• Try_get/can_get
• Returns 1 if it was able to retrieve or
could get an object

• Try_peek/can_peek
• Similar to get but doesn’t destroy
the object

7 02/07/2025 Intel Confidential


UVM TLM Methods – Blocking Example

8 02/07/2025 Intel Confidential


UVM TLM Methods – Non-blocking Example

9 02/07/2025 Intel Confidential


TLM Ports, Exports and Imps

• Port to Export
• Connecting components at
the same hierarchy(peer-to-
peer)

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TLM Ports, Exports and Imps

• Port to Export
• Connecting component ports
at the same hierarchy(peer-
to-peer)
• Port to Port
• Connecting child component
port to the parent
component port

11 02/07/2025 Intel Confidential


TLM Ports, Exports and Imps

• Port to Export
• Connecting component ports
at the same hierarchy(peer-
to-peer)
• Port to Port
• Connecting child
component’s port to the
parent component’s port
• Export to Export
• Connecting parent
component’s export to the
child component’s export

12 02/07/2025 Intel Confidential


TLM Ports, Exports and Imps

• Port to Export
• Connecting component ports
at the same hierarchy(peer-
to-peer)
• Port to Port
• Connecting child
component’s port to the
parent component’s port
• Export to Export
• Connecting parent
component’s export to the
child component’s export
• Lowest level export is actually an
Imp

13 02/07/2025 Intel Confidential


Sequence <--> Sequencer <--> Driver

Pull mode
• Sequence calls
wait_for_grant() which is
blocking
• Driver’s get_next_item(txn)
unblocks the sequence
• Transaction can be
randomized and
send_request(txn) pushes the
transaction
• Driver unblocks and receives
the transaction
• Sequence is blocked by
wait_for_item_done() which is
unblocked once driver calls
item_done()

14 02/07/2025 Intel Confidential


Sequence <--> Sequencer <--> Driver

Push mode
• Requires a special sequencer, driver i.e
uvm_push_sequencer, uvm_push_driver to support the push
mode

• Uvm_push_sequencer supplies the blocking put port while the


uvm_push_driver contains the blocking put imp and virtual
put() task

• Currently active sequence initiates the transaction by pushing


across the interface

• Can block in the driver depending if it can accept new


transactions

• Performance benefit?

15 02/07/2025 Intel Confidential


Analysis Ports

• Support 1:many
connections/subscribers

• Non-blocking function write()


called in zero time

• Primarily used in analysis


components
• uvm_subscriber has built-in
analysis_export

16 02/07/2025 Intel Confidential


Subscribers

• Derived from uvm_subscriber


class

• Contains uvm_analysis_imp and


pure virtual write() method

• Receives a pointer to the


transaction

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TLM FIFO

• Isolates producer-consumer
execution

• Implements all TLM methods –


put(), get(), peek()

• Infinite buffer depth

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Analysis FIFO

• Extended from the uvm_tlm_fifo


class

• Provides an analysis export


• Act as an analysis subscriber
• Built-in write()
implementation

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TLM FIFO Example

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Analysis FIFO Example

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Subscriber with Analysis FIFO

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Analysis of Multiple Streams

Option 1:
• Use macros for imp suffixes
• Can’t synchronize between
streams

Option 2:
• Use embedded analysis fifos
• Actively pull from fifos to
synchronize

23 02/07/2025 Intel Confidential


TLM 2.0

• TLM2 focuses on bus-based communication


• Uses sockets which contain both a port and an export
• Pass-by-reference
• Connections are between sockets
• Initiator socket connects to target socket

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TLM 2.0 – Blocking vs Non-blocking Transport

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UVM TLM – Summary & References

• Every port must eventually connect to an implementation(imp)


• We mostly care about only 2 port/export connections
• Sequencer-Driver: driver.seq_item_port.connect(seqr.seq_item_export)
• Analysis components:
monitor.analysis_port.connect(subscriber.analysis_export)

Doulos – UVM Adopter Class: https://


www.doulos.com/content/training/systemverilog_uvm_adopter.php
Verification Academy – Advanced UVM(How TLM Works): https://
verificationacademy.com/sessions/how-tlm-works
Testbench.in – UVM(Sequencer Driver communication): http://
www.testbench.in/UT_07_UVM_SEQUENCE_1.html

26 02/07/2025 Intel Confidential

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