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Timing Models

Timing models are essential for providing accurate timing for various instances of cells in design environments, specifying delays for timing arcs. Two types of timing models are discussed: Linear Timing Models, which use linear functions for delay calculations, and Non-Linear Delay Models (NLDM), which utilize table models for timing checks. The document also covers timing arcs for combinational and sequential cells, detailing setup, hold, recovery, and removal check arcs.

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13 views11 pages

Timing Models

Timing models are essential for providing accurate timing for various instances of cells in design environments, specifying delays for timing arcs. Two types of timing models are discussed: Linear Timing Models, which use linear functions for delay calculations, and Non-Linear Delay Models (NLDM), which utilize table models for timing checks. The document also covers timing arcs for combinational and sequential cells, detailing setup, hold, recovery, and removal check arcs.

Uploaded by

nalevihtkas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TIMING MODELS

Submitted by
HARSHITHA G H
TIMING MODELS
 Provide accurate timing for various instances of the
cell in design environment.
 The timing models are specified for each timing arc
of the cell.
 Define the delay arcs between nodes
Timing arc delays for an inverter cell

Since it is an inverter, a rising (falling) transition at the input


causes a falling (rising) transition at the output. The two kinds of delay
characterized for the cell are:
• Tr : Output rise delay
• Tf : Output fall delay
Delay for timing arc through inverter cell is dependent
on two factors:
1. the output load, that is, the capacitance load at the
output pin of the inverter
2. the transition time of the signal at the input.
 Delay increases with load capacitance, input

transition time.
Two types of Timing models
 Linear Timing Models

 Non-Linear Delay model


Linear Timing Model
 The delay and output transition time of cell are the
linear functions of the two parameters.
 Input transition time and Output load capacitance.
 Example
D=D0+D1*S+D2*C
Where D is delay of Linear model
D0,D1,D2 – Constants S – Input transition time
C – Output load capacitance
Non-Linear Delay Model
 cell libraries include table models to
specify the delays and timing checks for
various timing arcs of the cell.
 The table models are referred to as NLDM
(Non-Linear Delay Model) and are used
for delay, output slew, or other timing
checks.
In this example
 Delay of the output pin
OUT are described.
 Rising and falling delay
models for the timing arc
from pin INP1 to pin
OUT and max_transition
at pin OUT.
 Separate models for the
rise and fall delays,
labeled as cell_rise and
cell_fall respectively.
 Can also be used for
transition time at the
output of a cell.
Timing Models-Combinational cells
 In general, the timing arcs can
be from each input to each
output of the block
 logic path from input to output
is non-inverting(positive unate),
then the output has the same
polarity as the input
 If it is an inverting logic path or
negative unate, the output has
General combinational block
an opposite polarity to input
Timing Models – Sequential cells
For synchronous inputs – timing
arcs:
 Setup check arc (rising and

falling)
 Hold check arc (rising and

falling)
For asynchronous inputs – timing
arcs
 Recovery check arc

 Removal check arc


Reference:
Static Timing Analysis for Nanometer Designs
by J. Bhasker

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