Chapter Three

Memory and I/O Interfacing

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 Outline
 Memory Classifications
 Flip-Flop or Latch as a storage Element Memory Map and Addresses
Memory Instruction Fetch
 Memory Interfacing:
 Memory Structure & it’s Requirements Basic Concepts in Memory
Interfacing and Interfacing Circuits
 Address Decoding & Memory Address
 Input & Output Devices: I/Os with 8-Bit Addresses, I/Os with 16-Bit
Addresses
 Logic Devices for Interfacing Tri-State Devices buffer
 Encoders & Decoders Interfacing of I/O Devices: Basic Interfacing
Concepts Interfacing Output Displays Interfacing Input Devices
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 Memory Classification
 The memory is made up of semiconductor material used
to store the programs and data
 The memory is used to store information used by the
CPU.
 The information may be in the form of program or data.
 Memory can be classified into two groups.
1.Primary Memory
2.Secondary Memory

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1-Primary Memory
 It is a storage which can be directly accessed by the CPU.
 A CPU having n address line can access 2n memory location.
 The total primary memory area is partition into two separate sections
called the ROM area and RAM area
A. ROM
 The data cannot be written over and can only the read.
 The ROM is used to store information that should not change
 On power on or a reset, CPU always starts executing program from a
fixed default address which is first address of the address space.

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 ROMs are available into 4 types. There are

i. Masked ROM ii. PROM iii. EPROM iv. EEPROM

i-Masked ROM : instructions are permanently installed by manufacturer as for
the specification provided by system programmer and cannot be altered.
ii-PROM (Programmable Read Only Memory)
 The manufacturer provides a memory device which can be programmed by
the user
iii-EPROM (Erasable PROM)
 It uses most charge storage technology.
 It is also programmable by the user.
 The information stored can be erased by exposing the memory to ultraviolet
light
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iv-EEPROM (Electrically Erasable PROM)
 Data is erasing by electrical control software
B. RAM(Read/Write Memory)
 It’s working area of CPU
 The CPU can access any memory location by specifying its address.
 RAMs are two types.
 Static RAM
 It store bits as voltage
 Low density but high speed
 It uses flip-flops for storage elements.
 More expensive and consume more power
 No refresh periodically 6
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ii-Dynamic RAM
 It store bits as charge
 It has high density and low power consumption .
 Cheaper than SRAM
 contents of dynamic RAM may change with time due to leakage of
charge.
 It is periodically refresh the storage element
 It has 5 times more storage element per unit area.
 slower access times and need special circuitry to periodically refresh
memory.

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2. Secondary Memory
 storage devices used to store data permanently
 It has a much larger storage capacity than primary memory but slower
access speeds.
 It is non-volatile, meaning data is retained even when the power is turned
off.
 The CPU cannot directly access memory but can access through I/O ports.
 E.g. magnetic tapes, hard disk, and floppy disk.

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 Memory Mapping
 8085 has 16-bit Address Bus
 Complete address space range of addresses is 0000H –FFFFH
 The range of addresses allocated to a memory device is called memory
map
Memory map: 64K memory device
I. Address lines required: 16 (A0 – A15)
II. Memory map: 0000H – FFFFH
Memory map: 32K memory device
 Address lines required: 15  (A0 – A14)
 Memory map: depends on how address line A15 is connected
 Address line: the physical connection between CPU and memory

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ROM Model:
 The CPU outputs the binary address to access a specific word in ROM.
 A decoder is placed between the CPU and ROM to convert the address
into a unique activation signal for the selected word
 Only one word is activated at a time based on the address.
 E.g. for a 3-bit address (n=3), there are 28 possible memory locations
 When the CPU sets the address lines 𝐴2,𝐴1,𝐴​ to 111, it is requesting
access to the memory cell at binary address 111, which corresponds to
the 8th memory cell(address 7, assuming counting starts from 0).
 The decoder interprets the address 111 and activates the memory cell B7
 The word 𝑊(7) stored in B7 is organized as 𝑊2(7)𝑊1(7)𝑊0(7)
representing different parts of the data placed in data bus

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RAM Or Read/Write Model:
 internal organization of a (RAM) is similar to ROM.
 RAM allows both reading from and writing data to memory.
 Data is accessed (read) from a specified address.
 Data is written to a specified address, with a write-enable signal activating the
process
 Typically organized in rows and columns, with a decoder to select the address
and an encoder to output data
 It is faster than secondary storage, used for temporary storage of data that
needs quick access during processing

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 Interface
 Interface is the path for communication between two components.
 Interfacing is two types,
1. memory interfacing
2. I/O interfacing.
1. Memory Interfacing:
 is the connecting memory units(RAM and ROM) with a microprocessor to
enable reading and writing data
 Designing an interfacing circuit involves ensuring:
 memory and microprocessor signals are compatible
 timing of data transfers is synchronized
 Memory interfacing and address decoding is the connecting of memory devices
to microprocessor and determining the specific memory location being accessed

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 Memory interfacing has three steps
 Select chip
 microprocessor places a 16-bit address on the address bus and address bus
selects the memory chip, and part of address is decoded to identify the
specific register within the chip
 Identify the Memory Register:
 signals IO/M and RD/WR are used to show whether a memory read or write
operation is in progress e.g. for reading IO/M=0 and RD=0
 Enable Appropriate Buffer
 MEMR signal is used to enable the RD line on memory chip, allowing data
to be transferred from memory to microprocessor
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 Memory structure & its requirements
 The method of interfacing the two chips with the microprocessor is
same. However, the ROM does not include a WR signal

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Overall Interface

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 I/O Interfacing
 It is connecting peripheral devices to a computer or microprocessor, allowing
communication between the system and external devices
 e.g. Keyboards, mouse, printers, monitor etc.
 Keys aspect of interfacing
 Ports the interface for connecting I/O devices
 Control Signals managing communication (e.g., Read, Write signals)
 Data Transfer: Methods for sending and receiving data between the processor and
I/O devices

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 8085 I/O addressing
 I/O devices can be interfaced using addresses from memory space
 8085 treats such an I/O device as a memory location is called Memory-mapped
I/O
 8085 has a separate 8-bit addressing scheme for I/O devices, this is called
Peripheral-mapped I/O or I/O-mapped I/O
 I/O address space ranges from 00H to FFH
 8085 Communication with I/O device
 Involves the following three steps
1. Identify the I/O device (with address)
2. Generate Timing & Control signals
3. Data transfer takes place
 8085 communicates with a I/O device only if there is a Program Instruction to do
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1. Identify the I/O device (with address)
a. Memory-mapped I/O (16-bit address)
b. Peripheral-mapped I/O (8-bit address)
2. Generate Timing & Control signals
 Memory-mapped I/O
 Reading Input: IO/M = 0, RD = 0
 Write to Output: IO/M = 0, WR = 0
 Peripheral-mapped I/O
 Reading Input: IO/M = 1, RD = 0
 Write to Output: IO/M = 1, WR = 0
3. Data transfer takes place

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 Input/output devices can be interfaced with microprocessor systems in two ways:
1. Memory Mapped I/O Scheme
2. I/O Mapped I/O Scheme
1. Memory Mapped I/O Scheme
 I/O devices are identified by 16-bit addresses
 Microprocessor treats I/O devices like memory locations.
 Address space is the set of all possible addresses that a microprocessor can
generate
 Some addresses are assigned to memories, while others are assigned to I/O
devices
 The addresses assigned to I/O devices are different from assigned to memory
 Each I/O device is assigned a unique address
 All data transfer instructions in both memory and I/O devices is identical
 This scheme is suitable for small systems 20
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2. I/O Mapped I/O Scheme
 The addresses assigned to memory locations can also be assigned to I/O
devices.
 To differentiate whether the address on an address bus is for a memory location
or an I/O device,
 the Intel 8085 uses the IO/M signal:
 When the signal is high, the address bus is for an I/O device
 When the signal is low, the address is for a memory location
 In 8085 MP has two instructions for data transfer b/n the processor and I/O
devices
 IN: Reads data from an input device
 OUT: Sends data to an output device
 This scheme is suitable for large systems 21
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 Interfacing of Output Devices
 Output devices usually operate slowly and need to display output for an
extended period.
 Because the data is present on the data lines for only a very short period
(microseconds), it must be latched externally.
 To do this, the external latch should be enabled when the port's address is on
the address bus
 the IO/M signal is high, and the WR signal is low
 This resulting signal will be active when the microprocessor accesses the
output device.
 Interfacing of Input Devices
 The basic concepts are similar to interfacing of output devices.
 The address lines are decoded to generate a signal that is active when the
particular port is being accessed
 An IORD signal is generated by combining IO/M and the RD signals from the
microprocessor.
 A tri-state buffer is used to connect the input device to the data bus.
 The control (Enable) for these buffers is connected to the result of combining the
address signal and the signal IORD.
End of chapter Three
Any Question???

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