Microprocessor

CE– 2024-25 – Microprocessor

Kranti Bade
Assistant Professor
Dept. of Computer Engineering,
SIES Graduate School of Technology

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Prof. Kranti Bade
Detail Syllabus Content Continue……
Module Detailed Content Hours
1 The Intel Microprocessors 8086 Architecture
1.1 8086 CPU Architecture, 8
1.2 Programmer’s Model
1.3 Functional Pin Diagram
1.4 Memory Segmentation
1.5 Banking in 8086
1.6 Demultiplexing of Address/Data bus
1.7 Functioning of 8086 in Minimum mode and Maximum
mode
1.8 Timing diagrams for Read and Write operations in
minimum and maximum mode
1.9 Interrupt structure and its servicing

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History of Microprocessor

Intel 4-Bit 4004 1971 First

microprocessor
Intel 8-Bit 8008 1972 Low performance
and their design

Intel 8-bit 8080 1974 Advanced

microprocessor
Intel 8-Bit 8085 Added Features in
8080
Functionally
complete
architecture
8-Bit microprocessors were very low speed , low memory addressing capability, limited number of
general purpose registers and less powerful instructions set.

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First 16-Bit microprocessor

Intel 8086 was the first 16-Bit microprocessor to be launched in 1978.

8086 Microprocessor

• More powerful and high speed computational resources.

• Instruction set along with architectural developments which imparts substantial programming
flexibility and
• Improvement in speed over 8-Bit microprocessor.
• Peripheral chips designed earlier for 8085 were compatible with 8086 microprocessor with small
modifications.
• Memory interfacing technique is similar but includes use of few additional signals.

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Important Features of 8086

1. Buses
Address Bus : 8086 has a 20 bit address bus , hence it can access 2 20 Byte
memory i.e. 1 MB. The
address range for this memory is 00000H ………….FFFFFH.

Data bus: 8086 has a 16-bit data bus. i.e . It can access 16-bit data in one operation. Its ALU and
internal data registers are also 16-Bit. Hence 8086 is called as a 16- Bit microprocessor
Control Bus: The control bus carries the signals responsible for performing various operations as
RD, WR etc

2. 8086 supports Pipelining.

It is the process of “Fetching the next instruction ,while executing the current instruction” Pipelining
improves performance of the system”.

3. 8086 has 2 operating modes.

1. Minimum mode: here 8086 is the only processor in the system.(uni-processor).
2. Maximum mode…..here 8086 with other processors like 8087-NDP/8089-IOP etc.

4. 8086 provides memory Banks.

The entire memory of 1MB is divided into 2 banks of 512kB each, in order to transfer bits
in 1 cycle . The banks are called as Lower Bank(even) and Higher Bank(Odd).

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5. 8086 supports Memory segmentation.

Segmentation means dividing the memory into logical components. Here the memory is divided into 4
segments : Code, Stack, Data and Extra segment.

6. 8086 has 256 interrupts.

The ISR addresses for these interrupts are stored in the IVT (Interrupt Vector Table).

7. 8086 has a 16-Bit IO address: It can access 2^16 IO ports(2^16 = 65536 i.e. 64k IO ports).

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8086 Architecture

As 8086 does 2- Stage pipelining , it’s architecture is divided into two units.
1. Bus interface Unit (BIU)
2. Execution Unit(EU)

Bus Interface Unit

3. It provides interface 8086 to the other devices.

4. It operates w.r.t Bus cycles.
5. This means it performs machine cycles such as Memory read, IO write etc to transfer data with
Memory and IO devices.
6. The BIU contains circuit for physical address calculations and predecoding instruction byte
Queue (6 byte long)
7. This unit makes the system’s bus signals available for external interfacing of the devices.
8. 8086 addresses segmented memory.
9. The complete physical address which is 20bits long is generated using segment and offset
registers.

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11111H

DS
00111H

CS
00011H

00000H

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Bus interface unit
The main components of BIU are as follows.
a) Segment registers
1. CS register: it hold base (segment) address for the code segment.
All programs are stored in the code segment.
It is multiplied by 10H (16d) , to give 20-bit physical address of the code segment.
e.g. if CS = 4321H the CS * 10H = 43210H  starting address of code segment.
CS register cannot be modified by executing any instruction except branch instructions.

2. DS register: it hold base (segment) address for the Data segment.

It is multiplied by 10H (16d) , to give 20-bit physical address of the data segment.
e.g. if DS = 4321H the DS * 10H = 43210H  starting address of data segment.

3. SS register: it hold base (segment) address for the stack segment.

It is multiplied by 10H (16d) , to give 20-bit physical address of the stack segment.
e.g. if SS = 4321H the SS * 10H = 43210H  starting address of stack segment.

4. ES register: it hold base (segment) address for the Extra segment.

It is multiplied by 10H (16d) , to give 20-bit physical address of the extra segment.
e.g. if ES = 4321H the ES * 10H = 43210H  starting address of extra segment.

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b) Instruction register (IP register)
It is 16-bit register.
It holds offset of the next instruction in the code segment.

C) 6- Byte Pre-Fetch Queue (Pipelining)

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d)
The BIU contains circuit for physical address calculations

Physical address = Segment address * 10H + Offset address

The segment address is shifted by 4 positions , this multiplies the number by 16(i.e. 10H) then offset
address is added

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Calculate physical address(effective address)

Data segment register (DS) = 1000H

10050H

Offset address= 0050H Offset

Physical address = ?
10000H

DS value 1000H Multiply by 10H OR shift to left by 4

positions

0001 0000 0000 0000 0000 segment base address

+ 0000 0000 0101 0000 offset address
_____________________________
0001 0000 0000 0101 0000 H physical address of data

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Execution Unit

It fetches instructions from the Queue , decodes and executes them

It performs arithmetic, logic and internal data transfer operations.
It sends request signals to the BIU to access external module.
It operates w.r.t T-states(clock cycles)

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General Purpose Registers
8086 has 16- bit registers AX,BX CX and DX

AX- 16 Bit accumulator, with lower 8-bit AX designated as AL and higher 8-bits as AH. AL can be
used as an 8-Bit accumulator for 8 bit operations.
BX – is used as an offset storage for forming physical addresses in case of certain addressing
modes.
CX – is used as default counter register in case of string or looping instructions.
DX – may be used as an implicit operand or destination in case of a few instructions.

Special Purpose registers: Pointers and Index registers

Pointers contain offset within particular segment. The pointers IP,BP and SP usually contain
offset within code (IP) and stack segments(BP and SP)

Stack Pointer (SP):

Base Pointer (BP):
Source Index(SI):
Destination Index(DI):
ALU
Operand register

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Thank You!
([email protected])

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