System on a Chip

• An IC that integrates multiple components of a

system onto a single chip.
• MPSoC addresses performance requirements.

Introduction to SoC Design 1

 System on a Chip
On-Chip Components?
A processor or multiple processors
* Including DSPs, microprocessors, microcontrollers
Cores (IPs): On-chip memory, accelerators,
peripherals (i.e. USB, ETH, etc.), PLLs, power
management, etc.

Introduction to SoC Design 3

 Technology Roadmap in the past

H.P: High performance µP -

MicroProcessor H.H: Hand Held
Devices
Introduction to SoC Design 6
 Evolution: Boards to SoC
Evolution:
•IP based design
•Platform-based design
Some Challenges
•HW/SW Co-design
•Integration of analog (RF) IPs
•Mixed Design
•Productivity
Emerging new technologies
•Greater complexity
•Increased performance
•Higher density
•Lower power dissipation

Introduction to SoC Design 7

 SC2A11: Multi-core Processor
A multi-core processor SoC with 24-
cores of ARM Cortex-A53.
SC2A11 suitable for low-power server
systems. It can also suit to edge
computing to process data at the edge
of the cloud.

Introduction to SoC Design 8

 ASIC to System-on-Chip
ASICs: Application Specific ICs are close to SoC designed to
perform a specific function for embedded and other
applications.
*ASIC vendors supply libraries for each technology they provide.
Mostly, these libraries contain pre-designed/verified logic circuits.
*SOC is an IC designed by combining multiple stand-alone VLSI
designs to provide a functional IC for an application. It composes
of pre-designed models of complex functions e.g. cores (IP block,
virtual components, etc.) that serve various embedded
applications.

Introduction to SoC Design 9

 ASIC Design Flow
Top Level
Design
Long Time to Design
Unit Block Design DVT: Design,
Unit Block Verification Verification
Integration and Synthesis and Testing
Trial Netlists
Timing Convergence
& Verification

System Level Verification

Fabrication

DVT Prep

DVT
5 10 10 4 13 ?? 4 6 Time in Weeks

42
Time to Mask order
52

Introduction to SoC Design 10

 System-on-Chip Design Flow
• Specify: What does the customer really want?
• Architect:
* Find the most cost and performance effective
architecture to implement it?
* Which existing components can we adapt &
re-use?
•Evaluate: What is the performance impact of a
cheaper architecture?
•Implement: What can we generate automatically
from libraries and customization?
Use separate computation, communication, etc.
Introduction to SoC Design 11
 SoC Design Flow
SoC -- Typical Design Steps
Top Level •Due to Chip Complexity
Design
Unit Block Design
Unit Block Verification
and lower IC area, it is
Integration and Synthesis important to reduce
Trial Netlists
Placement, Layout and
Timing Convergence Fabrication steps time.
and Verification
•There is need to reduce the
System Level
Verification time of other steps before
Fabrication
Placement, Layout and
DVT Prep
Fabrication steps.
DVT •One should consider Chip
3 3 2 12 4 4
Time in Weeks
Layout issues up-front.
20 Time to Mask order
28

Introduction to SoC Design 12

 System-on-Chip

CPU

MPEG CORE

DSP

GPU

Analog Other Component

RF

Introduction to SoC Design 13

 SOC Structure
A tile of the chip

Cache
L2
p2
contr
ol
Switc
h dat
p Fabric p a
3 Contr 1
ol parit
p
Logic 0
p y
4
spar
Networ Data
k $ e
Interfac Instr
Switc e $
h cor
Fabric
e
Contr
ol p
Logic 0

bus
Network p1 p3

Data $ Interface
Instr
$
A communication link
core

A computational
block
Introduction to SoC Design 14
 SOC: System on Chip
 SOC cannot be considered as a large ASIC
 Architectural approach involving significant design reuse
 Addresses the cost and time-to-market problems
 SOC design is significantly more complex
 Need cross-domain optimizations
 IP reuse will increase productivity, but not enough
 Even with extensive IP reuse, many of the ASICs design
problems will remain, and more …
Proc IP cores

Mem Mem

IP- USB USB

CPU Sec hub CPU hub
DSP
$100 $10
IP- X
Co-
DSP X Sec Proc

Introduction to SoC Design 15

A SOC design has to deal with a wide range: it starts with a functional
description on system level, where major function blocks are defined
and no timing information is given. The other end of the spectrum is
the result of the design process, where all functionalities described
before are mapped to hardware and all hardware is defined down to
the RTL level. At that point in time a cycle accurate model exists,
which is ready for production.
 SOC Applications
 SOC Design include embedded processor cores, and a
significant software component, which leads to
additional design challenges.
 An SOC is a system on an IC that integrates software and
hardware Intellectual Property (IP) using more than one
design methodology.
 The designed system on a chip is application specific.
Microprocessor, Media
Typical applications of SOC: processor,
GPS controllers,
 Consumer devices. Cellular/Smart
phones, ASICs,
Consoles, PC-on-a-
HDTV,
 Networking and communication.
Game
chip
 Biomedical Devices.
 Other segments of electronics industry.

Introduction to SoC Design 17

 IP: Intellectual Property Cores
IP cores can be classified into three types:
Hard IP cores are hard layouts using physical design
libraries. The integration of hard IP cores is simple and easy.
However, they are technology dependent and lack
flexibility.
Soft IP cores are generally in VHDL/Verilog code providing
functional descriptions of IPs. These cores are flexible and
reconfigurable. However, these soft IP cores must be
synthesized and verified by the user before integrating them.
Firm IP cores provide the advantage of both balancing the high
performance and optimization properties of hard IPs along with
the flexibility of soft IPs. These cores are provided in the form
of netlists to specific physical libraries after synthesis.
Introduction to SoC Design 18
 Some IP Examples

Introduction to SoC Design 19

 Multi-Core (Processor) System-on-Chip
Inter-node communication between CPU/cores can be
performed by message passing or shared memory.
Number of processors in the same chip-die increases at
each node (CMP and MPSoC).
• Memory sharing will require: Shared Bus
* Large Multiplexers
* Cache coherence
* Not Scalable
• Message Passing: NOC: Network-on-Chip
* Scalable
* Require data transfer transactions
* Overhead of extra communication

Introduction to SoC Design 20

 Buses to Networks

• Architectural paradigm shift: Replace wire spaghetti by

network
• Usage paradigm shift: Pack everything in packets
• Organizational paradigm shift
 Confiscate communications from logic designers
 Create a new discipline, a new infrastructure responsibility
Introduction to SoC Design 29
 MPSoC
MPSoC is a system-on-chip and it contains multiple
instruction-set processors (CPUs).
• A typical MPSoC is a heterogeneous
multiprocessor where several different types of
processing elements (PEs).
• The memory system may also be heterogeneously
distributed around the machine, and the
interconnection structure between the PEs and the
memory may also be heterogeneous.
• MPSoCs often have large memory. The application
device can have embedded memory on-chip, and may
rely on off-chip commodity memory.
Introduction to SoC Design 22
NOC and SOC Design 34