School of Computer Science and Electronic Engineering

CE162 - Digital Electronic Systems

Section 2 - Combinational Digital Circuit Design

*From original source material by Tim Dennis

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Combinational Circuits
• The fundamental property of a Combinational Circuit is that its output(s) depend only on the current state of its inputs
within the limits of physical propagation delays. This is in contrast to sequential circuits (also known as Finite State
Machines) where the current output of the circuit depends on current inputs and previous outputs.

• Combinational circuits can be implemented in two main ways: using Logic Gates or Lookup Tables (memory). We
concentrate for now on logic gate implementations.

• The specification for a combinational circuit typically starts with a Truth Table, which specifies exactly how each output
depends on all possible combinations of the inputs.

• The design process can be done using Boolean Algebra alone, or Boolean Algebra in combination with Karnaugh
Maps.

Inputs Outputs
X1(t) Z1(t)
X2(t) Z2(t)
COMBINATIONAL LOGIC
CIRCUIT

Xn(t) Zm(t)

At time t, for any output j, 1 ≤ j ≤ m,

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 Representing Logic Signals
An electronic logic signal is assumed to take one of two possible levels, and there are two possible
interpretations:

Positive Logic: Negative Logic:

Low: Logic 0 FALSE Low: Logic 1 TRUE
High: Logic 1 TRUE High: Logic 0 FALSE

Although the Positive convention is most often used, Negative is also common and sometimes helpful.

Using the terms 'High' and 'Low' gives an unambiguous description of the electronic behaviour of a logic device.
Depending on the interpretation, the 'logical' behaviour can be very different.

Physical Voltage Levels To be interpreted as a valid logic level, the signal voltage must lie
within the upper or lower bands: this allows for the unavoidable
V(H) max errors and interference that will occur in practical systems. It is up
to the system designer to ensure that the signals really do fit
HIGH = binary 1
within the specification.
V(H) min
Device manufacturers will give figures for V(H) min and V(L) max;
Undefined: transition region if your signal does not lie above or below these values when it
Voltage
Signal

should, the circuit may still work but it is not guaranteed!

V(L) max
LOW = binary 0 For example, the data sheet for a commonly-used TTL
V(L) min logic device specifies V(H) min = 2 V, V(L) max = 0.8 V.

The nominal TTL High and Low voltage levels are +5 V (the power
supply voltage) and 0 V respectively.

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The Basic Logic Functions – NOT gate (inverter)

Truth Table Logical Symbols (used in circuit diagrams)

Input, A Output, Z Input A 1 Output Z

0 1
1 0

Boolean representation:

This would be read as 'Z equals not A'.

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 The Basic Logic Functions – AND gate

Logical Symbols
Truth Table

A
& Z
Inputs Output B

A B Z
0 0 0
0 1 0 A
Z
1 0 0 B
1 1 1

Waveform behaviour
Boolean Algebra representation:
Z= A . B A
or
B
Z= AB
This would be read as 'Z equals A and B'. The reason why the
notation is the same as arithmetic multiplication in 'ordinary'
algebra is because the outcome is effectively the same.
Z?
What is the Truth Table for a 3 (or more!) input AND gate?
How many rows in its Truth Table? 5
 The Basic Logic Functions – OR gate

Logical Symbols
Truth Table

A
≥1
Inputs Output B
Z
A B Z
0 0 0
0 1 1 A

1 0 1 B
Z
1 1 1

Waveform behaviour
Boolean Algebra representation:
A

Z= B
A+B
This would be read as 'Z equals A or B'. The reason why the
notation is the same as arithmetic addition in 'ordinary' algebra is
because the outcome is the same for all but A = B = 1.
Z?

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 The Basic Logic Functions – Exclusive OR gate (XOR)

Logical Symbols
Truth Table

A
=1 Z
Inputs Output B

A B Z
0 0 0
0 1 1 A
Z
1 0 1 B

1 1 0

Waveform behaviour
Boolean Algebra representation:
A

𝑍 = 𝐴⊕ 𝐵= 𝐴 . 𝐵+ 𝐴. 𝐵 B

The XOR gate is sometimes called a modulo 2 adder since it

computes the 'sum' bit of the arithmetic addition, A plus B.
Z?

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The Basic Logic Functions – NAND gate

Truth Table Logical Symbols

A
Inputs Output
& Z
A B Z B

0 0 1
0 1 1
1 0 1 A
Z
1 1 0 B

Boolean Algebra representation:

NAND (and NOR) gates are especially useful in practical circuit design because it is possible to implement
any combinational circuit using just one kind of gate. NAND gates are also very easy to manufacture: a
two-input NAND gate requires a minimum of two CMOS transistors. Because their implementation was so
simple, NAND gates were the preferred basic logic element in the bipolar Transistor-Transistor Logic family
(TTL).

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The Basic Logic Functions – NOR gate

Truth Table Logical Symbols

A
Inputs Output
≥1 Z
A B Z B

0 0 1
0 1 0
1 0 0 A
Z
1 1 0 B

Vcc (≈5 V)

Rc ≈ 470 ohm
Boolean Algebra representation:
Inputs
Z
𝑍 = 𝐴+ 𝐵 A

B
𝑍 = 𝐴 + 𝐵+ 𝐶
A multi-input NOR gate can be made with one npn bipolar C
transistor and some resistors.
Base resistors ≈22 kohm
What are the likely problems with this circuit in a practical 0V
application?
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Logic/Digital Signals - The ideal

Marks Space Period, T= 1/frequency

A 1 Z

Time

A
In a periodic digital waveform, it is common to
refer to its 'mark-to-space ratio': this indicates the
relative time spent at the High (logic 1) and Low
(logic 0) states.
Z

What are the durations in nanoseconds of Mark and

Space for a periodic waveform whose mark-to-space
ratio is 1:4 at a frequency of 5 MHz?

Non-periodic waveform

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 Waveform carrying continuous digital (binary) information
(the basis of all synchronous digital signal systems)

1 1 0 1 0 0 1 0 1 1 0 Bit (data) sequence

Signal

Clock

Reference timing edge

Although the data waveform looks non-periodic, in fact, signal transitions will occur at integer multiples
of the timing clock period. This information is used to 'recover' the timing waveform at a digital receiver
and avoids the need to transmit a clock waveform in parallel with the data waveform.

(Compare with asynchronous data transmission mentioned in Section 1, where the clock recovery
method is different.)

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 Logic/Digital Signals - The Practical: typical real world logic waveforms

The top line (C) is the 'signal' on the 5 V power line – where there should only be a steady DC supply voltage.

Waveform A is the LSB from a 3-bit counter. Its frequency is about 12 MHz.

Distortions arise mainly because of stray coupling between conductors, both capacitive and inductive, and because conductors
behave like 'transmission lines', an effect that becomes increasingly apparent at high frequencies.

Waveform B is the active LOW output of a circuit that detects 000 from the outputs of the counter. Note that it is delayed
slightly from waveform A – this always happens in any logic device, which all introduce propagation delay.

Finally, note that the waveforms do not change state 'instantaneously': in addition to propagation delay, there will also be a
finite rise time and fall time; these may not be the same. 12
The ideal and the practical
What would the output be for the squarewave input shown?

1 1 1
In & Out ?

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Combinational Circuit Design – Boolean Algebra fundamentals
a) Variables can assume one of two values only, represented as 0 or 1.

b) From the definitions of the basic logic operations AND, OR and NOT, the following tabulated statements can be derived, and
the laws below proved.
0 .0 = 0 0+
0=0
0 .1 = 0 0+
1=1
1 .0 = 0 1+0=1
1 .1 = 1 1+1=1
c) Laws of Boolean Algebra

i) Defining Law ii) Identity law iii) Commutative law

A+0=A A+A=A A+B=B+A

A+1=1 A.A=A A.B=B.A
A.0 =0
A.1=A
iv) Associative Law v) Absorption Law

(A + B) + C = A + (B + C) A+A.B=A
(A . B) . C = A . (B . C) A . (A + B) = A
vi) Distribution Law

(A . B) + (A . C) = A . (B + C)
(A + B) . (A + C) = A + (B . C)

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vii) Minimisation Theorems (useful when simplifying logic equations)

viii) De Morgan's Theorem – the fundamental relationship between AND and OR functions

In general, to find the complement of any Boolean expression, change AND to OR and
complement each sub-element of the expression.

A B A+B
Truth Tables for OR – same as AND of
0 0 0 1 1 1 the input variables complemented
0 1 1 0 1 0
1 0 1 0 0 1
1 1 1 0 0 0

A B A.B
Truth Tables for AND – same as OR of
0 0 0 1 1 1 the input variables complemented
0 1 0 1 1 0
1 0 0 1 0 1
1 1 1 0 0 0

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Using De Morgan's Theorem NAND gate revisited

(See Floyd, Digital Fundamentals (10th ed.), section 4.3)

Inputs Output
A B Z
0 0 1
Example (Floyd, p. 181)
0 1 1
1 0 1
Simplify:
1 1 0

A
Work downwards through the complement operators: first we & AB
complement the two halves of the expression and replace OR by B
AND:

A
≥1 A+B

Then deal with each sub-expression. Double complements B

simply cancel each other out:

These are the same. A useful way of thinking about

NAND gates is that they 'perform an OR operation
on ACTIVE LOW inputs'.

In practice they are very commonly used this way.

What is the equivalent interpretation of a NOR gate?

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 Inputs
A basic 4-input Logic Circuit
A
Output, Z
B
LOGIC
C CIRCUIT

Commonly-occurring logic element: AND-OR circuit ABCD A.B C.D A.B + C.D
0000 0 0 0

B
A A.B 0001 0 0 0
Z = AB + CD
& 0010 0 0 0
≥1
0011 0 1 1
C C.D
0100 0 0 0
D
&
0101 0 0 0
0110 0 0 0
Deriving the Truth Table
Composite symbol 0111 0 1 1

A 1000 0 0 0
& Z = AB + CD 1001 0 0 0
≥1 1010 0 0 0
B
& 1011 0 1 1
1100 1 0 1
C
1101 1 0 1
1110 1 0 1
D
1111 1 1 1

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Find the Truth Table for this...

A
& ABCD
B
0000 1 1 0
& 0001 1 1 0
C 0010 1 1 0

D
& 0011 1 0 1
0100 1 1 0
0101 1 1 0
0110 1 1 0
0111 1 0 1

Apply De Morgan's Theorem: 1000 1 1 0

1001 1 1 0
1010 1 1 0
1011 1 0 1
1100 0 1 1
1101 0 1 1
1110 0 1 1
1111 0 0 1

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Canonical Forms
Sum of Products (SoP) and Product of Sums (PoS)

Any logic function can be expressed as

i) the sum (+) of a number of product (.) expressions, or

ii) the product (.) of a number of sum (+) expressions

where each term contains each of the variables in complemented or uncomplemented form.

PoS functions can be done with two stages of NOR gates, while SoP expressions are implemented using two stages of
NAND gates. Since NAND gates are the commonest type, this form is often preferred:

A
&
B

& Z = A.B + C.D

D
&

The intermediate OR operation can be understood from the interpretation of the NAND gate as performing a

logical OR operation on ACTIVE LOW inputs.

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Logic Circuit to Boolean Expression

A
&
B A.B
A.B + C
≥1
C

&
B
1
≥1 The Expression for Z can be re-written: (multiply-out brackets)
B+D
D

but , hence:

or

or

Construct circuits for the alternative forms of the equation.

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Derive Truth Table for Z = ABD + BC + CD

1 2 3 4 5
ABCD ABD CD Z For each of columns 2-4, enter a '1' where the
0000 respective condition is true.
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

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Graphical Representation: Karnaugh Map

ABCD ABD CD Z
0000 0 0 0 0 CD 00 01 11 10
0001 0 0 0 0 AB
0010 0 1 0 1
0011 0 1 1 1 00 0 1 3 2

0100 0 0 0 0
0101 0 0 0 0 01 4 5 7 6

0110 0 0 0 0
0111 0 0 1 1 11 12 13 15 14
1000 0 0 0 0
1001 0 0 0 0 8 9 11 10
10
1010 0 1 0 1
1011 0 1 1 1
1100 0 0 0 0
1101 1 0 0 1 Note that the identifiers are not in natural binary counting
1110 0 0 0 0 order, but instead use the sequence 00, 01, 11, 10* in
which 1 bit only changes between adjacent rows or
1111 1 0 1 1
columns.

To plot the function for Z, enter a '1' in the appropriate

squares, zeros everywhere else.

*This is the first few bit patterns of a Gray Code, also called a
Reflected Binary Code, which can be of any word length,
and retains this one-bit change property.
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Graphical Representation: Karnaugh Map

D C
ABCD ABD CD Z
0000 0 0 0 0
0001 0 0 0 0
0010 0 1 0 1
0011 0 1 1 1 B
0100 0 0 0 0
0101 0 0 0 0
0110 0 0 0 0 A
0111 0 0 1 1
1000 0 0 0 0
1001 0 0 0 0 Alternative K-map format
1010 0 1 0 1
1011 0 1 1 1
1100 0 0 0 0
1101 1 0 0 1
1110 0 0 0 0
1111 1 0 1 1

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Gray Code Sequence

0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
Applications: a clue
?
? (Image from http://images.machinedesign.com/images/archive/talk3jpg_00000038653.jpg

What comes next?

What is the general rule?

What applications does it have?

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 Gray Code Sequence
 Convert the binary code 01010 to the corresponding Gray code

+ + + +
0 1 0 1 0

0 1 1 1 1

 Convert the Gray code 01111 to the corresponding binary code

0 1 1 1 1

+ + + +

0 1 0 1 0

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Graphical Representation: Karnaugh Map – So What?

ABCD ABD CD Z
0000 0 0 0 0 CD 00 01 11 10
0001 0 0 0 0 AB
0010 0 1 0 1 0 1 3 2
0011 0 1 1 1 00 0 0 1 1
0100 0 0 0 0 4 5 7 6
0101 0 0 0 0 01 0 0 1 0
0110 0 0 0 0
0111 0 0 1 1 12 13 15 14

1000 0 0 0 0 11 0 1 1 0
1001 0 0 0 0 8 9 11 10
1010 0 1 0 1 10 0 0 1 1
1011 0 1 1 1
1100 0 0 0 0
1101 1 0 0 1 K-map simplification involves grouping contiguous
1110 0 0 0 0 sets of one, two, four or eight 1s, choosing the largest
1111 1 0 1 1 possible number of 1s in each group. Overlaps do not
matter.

NOTE THAT THE EDGES WRAP ROUND!

Find the product term that defines each group. The

final expression is their sum.

There may be several ways of doing the groupings in

any one example, but not here.
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Example
Construct a K-map for and simplify the sum of products Boolean expression:

Z = F(ABCD) = ∑(1, 2, 3, 5, 6, 7, 11, 12, 13)

(Note that this is an alternative to the full Truth Table listing, and a shorthand way of writing:

Z = A.B.C.D + A.B.C.D + ...)

Z=?
CD 00 01 11 10
AB
00 0 1 3 2

01 4 5 7 6

11 12 13 15 14

10 8 9 11 10

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Summary

This section has covered:

• The basic logic gates, and some of their electrical properties: rise time, fall time,
propagation delay

• Digital Signals

• Laws and applications of Boolean Algebra. Simplification of Boolean Equations.

• Using De Morgan's Theorem – one kind of gate implements PoS or SoP expressions

• Logic Circuits – derivation of logic function and Truth Table from circuit

• Circuit/Truth Table representation and simplification using Karnaugh Maps

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