Chapter 5

Basic Computer Organization

and Design

1
Computer Organization 2
 Instruction Codes
A group of bits that tell the computer to perform a specific operation
(a sequence of micro-operation)

Basically the internal organization of a computer is

defined by:
Its internal registers
The timing and control structure
The set of instructions that it uses

cpe 252: Computer Organization 3

• The basic operational mode of digital system is
defined by the sequence of microoperations it
performs on data stored in its registers.
• A digital system can be instructed as what specific
sequence of operation it must perform.
• The user of a computer can control the process by
means of a program
• A program is a set of instructions that specify the
operations, operands, and the processing sequence

4
 Instruction Codes
• A computer instruction is a binary code that specifies a
sequence of micro-operations for the computer. Each
computer has its unique instruction set.
• The operation code of an instruction is a group of bits
that defines certain operations such as add, subtract,
shift, and complement
• Instruction codes and data are stored in memory
• The computer reads each instruction from memory
and places it in a control register
• The control unit interprets the binary code of the
instruction and proceeds to execute it by issuing a
sequence of micro-operations.
5
 Instruction Codes cont.
• The number of bits required for the operation
code depends on the total number of
operations available in the computer
• For 2n (or little less) distinct operations  n bit
operation code is required.
• For example: in six bit operation code, 110010
is assigned to the ADD operation. When this
operation code is decoded in the control unit,
the computer issues control signals to read an
operand from memory and add the operand to
a processor register.
6
 Instruction Codes cont.

Memory It’s an
ADD
operation
Op code
Control
110010?????????? Unit

Read instruction
from memory

7
 Instruction Codes
• The operation part of an instruction code
specifies the operation to be performed.
• An operation must be performed on some data
stored in processor registers or in memory
• An instruction code must therefore specify not
only the operation, but also the location of the
operands (in registers or in the memory), and
where the result will be stored
(registers/memory)

8
 Instruction Codes cont.
• Memory words can be specified in instruction
codes by their address
• Processor registers can be specified by
assigning to the instruction another binary code
of k bits that specifies one of 2k registers
• Each computer has its own particular
instruction code format.
• In this chapter we will consider a particular
instruction code to explain the basic
organization and design of digital computer.

9
 Instruction Codes cont.

• An instruction code is usually divided into

operation code, operand address, addressing
mode, etc.
• But, The simplest way to organize a computer
is to have one processor register (accumulator
AC) and an instruction code format with two
parts (op code, address)

10
 Memory 4096
15 12 1 0 word ,16 bits
1 per word 0
Opcode Address 15

Instruction Format
Instructions
15 0
(program)
Binary Operand

Operands
(data)

15 0

Processor register
(Accumulator AC)

The control reads a 16 bit instruction from the program portion of

the memory.
It uses the 12 bits address part of the instruction to read 16 bit
operand from the data portion of memory. It then executes the
operation specified by the operation code
 Instruction Codes
Indirect Address
• There are three Addressing Modes used for
address portion of the instruction code:
– Immediate: the operand is given in the address
portion (constant).
– Direct: the address points to the operand stored in the
memory
– Indirect: the address points to the pointer (another
address) stored in the memory that references the
operand in memory
• Hence,One bit of the instruction code can be used to
distinguish between direct & indirect addresses
12
 Instruction Codes
Indirect Address cont.
Instruction Format Effective
15 14 12 11 0 address
I Opcode Address

Direct Address Indirect address

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC
 Computer Registers
• Computer instructions are normally stored in consecutive
memory locations and executed sequentially one at a time
• The control reads an instruction from a specific address in
memory and executes it, and so on
• This type of sequencing needs a counter to calculate the
address of the next instruction after execution of the current
instruction is completed.
• It is also necessary to provide a register in the control unit for
storing the instruction code after it is read from memory
• The computer needs processor registers for manipulating data
and a register for holding a memory address.
• These requirements demands the register configuration shown
in the next slide.

14
 Registers in the Basic Computer
11 0
PC
11 0
AR Memory

15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

15
 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR
E
Adder
and
logic
AC 4 Computer Registers
LD INR CLR
Common Bus System
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

16
 Computer Registers
Common Bus System cont.
• S2S1S0: Selects the register/memory that would
use the bus
• LD (load): When enabled, the particular register
receives the data from the bus during the next
clock pulse transition
• E (extended AC bit): flip-flop holds the carry from
ALU
• DR, AC, IR, and TR: have 16 bits each
• AR and PC: have 12 bits each since they hold a
memory address
17
 Computer Registers
Common Bus System cont.
• When the contents of AR or PC are
applied to the 16-bit common bus, the four
most significant bits are set to zeros
• When AR or PC receives information from
the bus, only the 12 least significant bits
are transferred into the register
• INPR and OUTR: communicate with the
eight least significant bits in the bus
18
 Computer Registers
Common Bus System cont.
• INPR: Receives a character from the input device
(keyboard,…etc) which is then transferred to AC
• OUTR: Receives a character from AC and
delivers it to an output device (say a Monitor)
• Five registers have three control inputs: LD
(load), INR (increment), and CLR (clear)

19
 Computer Registers
Memory Address
• The input data and output data of the memory are
connected to the common bus
• But the memory address is connected to AR
• Therefore, AR must always be used to specify a
memory address
• By using a single register for the address, we
eliminate the need for an address bus that would
have been needed otherwise.
• Register  Memory: Write operation
• Memory  Register: Read operation (note that AC
cannot directly read from memory!!) 20
• Computer operation and micro-operation
• Computer operation
– Is the operation part in the instruction stored in
computer memory.
– It is in binary code
– The control unit receives the instruction from
memory and interprets the operation code bits. And
then issues a sequence of control signals to initiate
micro-operation in internal computer register.
• Micro-operations
– are little operations that would be issued to carry
out the hardware implementation of every computer
operation.
21
 Instructions of the basic computer
• The basic computer has three instruction code
formats. Each format has 16 bits.
• The operation code part of the instruction contains
three bits and the remaining 13 bits depends on the
operation code encountered.
• A memory reference instruction uses the 12 bits to
specify an address and one bit (the15 th) to specify the
addressing mode, I. I is equal to 0 for direct
addressing and equals 1 for indirect addressing.
• But the I will not be used as a mode for register
reference and input out instructions rather it would be
used to distinguish the type of non- memory
reference instructions. 0 for register transfer and 122for
 Computer Instructions
Basic Computer Instruction code format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions specifies An operation on the AC register. So

do not require any operand from the memory. The remaining 12 bits are used to
describe the kind of operation
(OP-code = 111, I = 0)
15 12 11 0

0 1 1 1 Register operation

Similarly the Input-Output Instructions do not require A reference to a memory

hence the remaning 12 bits Will be used to specify the type of input or out put
operation (OP-code =111, I = 1)
0
15 12 11
1 1 1 1 I/O operation

If the three opcode bits in the position 12 thought 14 are not equal to 111, then the
instruction is a memory reference type and the bit in position 15 is taken as the addressing
mode. If the 3 bit opcode is equal to 111, control then inspects the bit in position 15, if 23
it is 0,
the instruction is register reference type. If the bit is 1, the instruction is an input-output.
24
 BASIC COMPUTER
INSTRUCTIONS
Symbol
Hex Code
I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt
cpe 252: Computer off
Organization 25
 Timing & Control
• The timing for all registers in the basic computer is
controlled by a master clock generator
• The clock pulses are applied to all flip-flops and
registers in the system, including the flip-flops and
registers in the control unit.
• A separate control signal must be used to decide
which specific clock pulse will have an effect on a
particular register.
• Therefore, The clock pulses do not change the state of
a register unless the register is enabled by a control
signal (i.e., Load)

26
 Timing & Control cont.
• The control signals are generated in the
control unit and provide control inputs for the
multiplexers in the common bus, control
inputs in processor registers, and
microoperations for the accumulator
• There are two major types of control
organization:
– Hardwired control
– Microprogrammed control

27
 Timing & Control cont.
• In the hardwired organization, the control logic
is implemented with gates, flip-flops, decoders,
and other digital circuits.
• In the microprogrammed organization, the
control information is stored in a control
memory (if the design is modified, the
microprogram in control memory has to be
updated)

28
 The Control Unit for the basic computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I
D7 Control Control
logic outputs
gates
T15
T0

15 14 . . . . 2 1 0
4 x 16
Sequence decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Hardwired Control
Organization
The content of Instruction register (IR) determines which 29
micro-instructions to be performed
-The SC can be incremented or once in a while it can be cleared. It responds to
the positive transition of the clock and increments with every positive clock
transition, unless the CLR input is active.
-- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Note: on the positive clock transition marked by T4 the counter is cleared to 0.

this causes the timing signal T0 to be active instead of T5
30
the positive clock transition labeled T0 in the diagram will only trigger those
31
 Timing & Control cont.
• To fully comprehend the operation of the computer, it
is crucial that one understands the timing relationship
between the clock transition and the timing signals.
• Example, T0: AR←PC
– Transfers the content of PC into AR if timing signal T0 is
active
– T0 is active during an entire clock cycle interval
– During this time, the content of PC is placed onto the bus
(with S2S1S0=010) and the LD (load) input of AR is enabled
– The actual transfer does not occur until the end of the clock
cycle when the clock goes through a positive transition.
– This same positive clock transition increments the sequence
counter SC from 0000 to 0001
– The next clock cycle has T1 active and T0 inactive
32
 Instruction Cycle
• A program is a sequence of instructions stored
in memory
• The program is executed in the computer by
going through a cycle for each instruction (in
most cases)
• Each instruction in turn is subdivided into a
sequence of sub-cycles or phases

33
 .
Instruction Cycle cont
• In the basic computer each instruction cycle
consists of the following phases:
• Instruction Cycle Phases:
– 1- Fetch an instruction from memory
– 2- Decode the instruction
– 3- Read the effective address from memory if the instruction
has an indirect address
– 4- Execute the instruction
• Upon the completion of step 4 the control goes
back to step 1 to fetch, decode and execute the
next instruction.
• This cycle repeats indefinitely unless a HALT34
instruction is encountered.
Fetch and Decode
• Initially, the Program Counter (PC) is loaded
with the address of the first instruction in the
program.
• And The sequence counter SC is cleared to 0,
providing a decoded timing signal T0
• After each clock pulse, SC is incremented by
one, so that the timing signals go through a
sequence T0, T1, T2, and so on
• Therefore the fetch and decode operations can
be specified by a sequence of microoperation
of register transfer statements.
35
– T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR. Because it
is only AR that is connected to the address line of the
memory
– T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented.
– T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11),
I←IR(15)
• At time T2 the operation code in IR is decoded, the
addressing mode bit is transferred to flip-flop I, and
the address part of the instruction is transferred to
AR.
36
To provide the data path for the transfer of PC to AR the timing signal T0 =1 must
be applied on (S0S1S2=010) so that the content of PC can be place on the common
bus and again T0 must connected to the LD input control of AR register so that the
content of the bus can be transferred to the AR register.

T0: AR PC
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus 37
DETERMINE THE TYPE OF INSTRUCTION
the timing signal that would be actived after the decoding is T3 during which the control unit
determines the type of instruction that was just read from memory.

Note: if D7 =1 the instruction must be either register reference or input-output

if D7=0 the operation code must be one of the other seven values 000- 110 that specifies a
memory- reference instruction. Start
SC 

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR] – a memory reference instruction with an indirect address.

D'7I'T3: Nothing – but the sequence counter must be incremented to T 4
38
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in B0 ~ B11 of IR
- Execution starts with timing signal T 3
r = D7 I’ T3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11, the i th bit of IR. The control function is distinguished by one
Of the bits in IR(0-11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop) 39
• The control logic gates are used to control:
– Inputs of the nine registers
– Read and Write inputs of memory
– Set, Clear, or Complement inputs of the flip-flops
– S2, S1, S0 that select a register for the bus
– AC Adder and Logic circuit

40
• Control of registers- AD
– The control inputs of the registers are LD (load), INR (increment), and
CLR (clear)
– To control AR We scan all statements that change the content of AR:
• R’T0: AR  PC LD(AR)
• R’T2: AR  IR(0-11) LD(AR)
• D’7IT3: AR  M[AR] LD(AR)
• RT0: AR  0 CLR(AR)
• D5T4: AR  AR + 1 INR(AR)
Hence the Control Gates structure associated with AR

From bus AR To bus

D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D5
T4 41
 Control gates for Accumulator AC
Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC

8 circuit To bus
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC’ Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
rB5 : AC  AC + 1 cpe 252: Computer Organization
Increment 42
 Control gates for Accumulator AC
Gate structures for controlling
the LD, INR, and CLR of AC
From Adder 16 16 To bus
and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR

D2 LDA
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11

where p = D7IT3 (Input/Output Instruction)

r = D7 I’ T3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11, the i th bit of IR. 43