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EEET2481
Embedded Systems
Design and
Implementation
Tutorial 2 – Accompany Slides

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Attendance Check – Scan this QR

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Previous Lecture

• We discussed:

• The clock controller for the NUC140 MCU

• How to configuring registers, including:

• Register names
• Their roles
• Register bits

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Warm-up

• Configure the PLL register to have the input frequency from HXT (12 MHz) as a
clock source to generate and provide a 50 MHz clock signal via PLL core.

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Warm-up

1. Choose PLL factor NO=4

-> Use this to calculate values to put in PLLCON

OUT_DV = 0b11

2. Choose PLL factor NR = 3

 Use this to calculate values to put in PLLCON

IN_DV + 2 = 3

 IN_DV =1

 IN_DV = 0b1

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Warm-up

1. From NO=4 and NR = 3, we get NF=50

NF 1
𝐹 𝑂𝑈𝑇 =F 𝐼𝑁 . .
𝑁𝑅 𝑁𝑂

 Use this to calculate values to put in PLLCON

FB_DV + 2 = 50

 FB_DV = 48

 IN_DV = 0b11_0000

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Next...

• We will use these calculation in the next Tutorial 2

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Review - Bit Manipulation for
Masking

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Bit Manipulation for Masking

• How can we check the value of a bit
in a multiple-bit number if it is 0 or
1? 8-bit register A = 0b XXXX_1X10
Check if the value of the bit 2 is 1
-> Apply Bit manipulation to mask the
Step 1a & 1b
value of the bit (1<<2) -> result in 100 (our mask)
Step 1c
o Step 1 – Masking the bit out of the A & (1<<2)
original number XXXX_1X10
&
a. identify the bit location m 0000_0100
Result:
b. shift left 1 by m position 0000_0X00
c. AND the number with the shift left Step 2 – check the result
from step b • if(A & (1<<2) ) - if X = 1 ->
o Step 2 – Check the result from step if(true)

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Bit Manipulation for Masking (2)

• How can we check the value of a bit
in a multiple-bit number if it is 0 or
1? 8-bit register A = 0b XXXX_1X10
Check if the value of the bit 2 is 0
-> Apply Bit manipulation to mask the
Step 1a & 1b
value of the bit (1<<2) -> result in 100 (our mask)
Step 1c
o Step 1 – Masking the bit out of the A & (1<<2)
original number XXXX_1X10
&
a. identify the bit location m 0000_0100
Result:
b. shift left 1 by m position 0000_0X00
c. AND the number with the shift left Step 2 – check the result
from step b • if(!A & (1<<2) ) - if X = 0 ->
o Step 2 – Check the result from step if(true)

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Masking for Multiple Bits

• Masking can expand to multiple

bits 8-bit register A = 0b 1010_1111
Mask out value of the first 4 bits
A[7:4]

Step 1a & 1b
(0b1111<<0)
-> result in 1111_0000 (our mask)

Step 1c
A & (0b1111<<0)
1010_1111
&
1111_0000
Result:
1010_0000

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Configuring NUC140 Clock

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Steps for configuring MCU clock

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Example - NUC140 MCU clock configuration

• Task 1 - Configure the NUC140 MCU to use HXT (12 MHz) as a clock source to
generate and provide a 50 MHz clock signal to the microprocessor core via PLL
core.

• Task 2 - In the main program, toggle a GPIO pin and then measure its blinking
frequency to validate the success of the clock configuration

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Clock Routing Paths in NUC140 MCU

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Simplified Diagram

Example: configure the NUC140 MCU to use HXT (12 MHz) as a clock source to generate and provide a 50 MHz clock signal
to the microprocessor core.
• Input clock source is from HXT via PLLOUT
• Output clock is 50MHz

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Step 0 - Unlock protected registers

• As we are configuring some protected registers involving clocks, at the

beginning of the process, we must unlock these prior to writing new changes.

SYS_UnlockReg(); // Unlock protected registers

• We will lock registers once we complete.

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Step 1

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Step 1: Enable and configure clock sources

• Step 1A - since we want to use HXT

as the clock source, HXT must be CLK->PWRCON |= 1<<0;

enabled:

a. PWRCON[0] is set to 1.
#define HXT_STATUS 1<<0
b. Wait for HXT to be stable before we
while(!(CLK->CLKSTATUS & HXT_STATUS));
can configure.

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Struct Pointer

• A struct to contain all registers in a group of peripherals – for example CLOCK

o System Power Down Control Register – PWRCON CLK is the pointer
defined in the header file
o AHB Devices Clock Enable Control Register – AHBCLK to access the registers.
CLK has the type CLK_T.
o APB Devices Clock Enable Control Register – APBCLK
CLK_T is a typedef
o Clock Status Monitor Register – CLKSTATUS
structure containing the
o Clock Source Select Control Register 0 – CLKSEL0 clock controller registers
(uint32_t is to assign to
o Clock Source Select Control Register 1 – CLKSEL1 32-bit registers)
o Clock Source Select Control Register 2 – CLKSEL2

o Clock Divider Number Register – CLKDIV

o PLL Control Register – PLLCON e.g. CLK->PLLCON will

point to the PLLCON
o Frequency Divider Control Register – FRQDIV register.

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CLK_T Struct

structure CLK_T defined in “NUC100Series.h”

Starts from line 613

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Struct Pointer

• Check out more on Canvas at 3.4 | Lecturer 5B - Struct and Pointer

• We will use this approach for programming registers from now on

CLK->PWRCON |= 1<<0;

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Step 1: Enable and configure clock sources

• Step 1B – As we need to use PLL, we

will select HXT as input clock source CLK->PLLCON &= (~(1<<19));

for PLLOUT:

o PLLCON[19] is clear to 0

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Step 1: Enable and configure clock sources

• Step 1C – We are using normal mode

so: CLK->PLLCON &= (~(1<<16));

a. PLLCON[16] is clear to 0.

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Step 1: Enable and configure clock sources

• Step 1D – Calculate values for

registers to get the desirable output
frequency - 50MHz
• Since FIN is HXT=12MHz, you can
select NF=50, NR=3, NO=4
o PLLCON[8:0] is set to 48 (i.e.,
FB_DV=48NF=48+2=50)
o PLLCON[13:9] is set to 1 (i.e.,
IN_DV=1NR=1+2=3)
o PLLCON[15:14] is set to 3 (i.e.,
OUT_DV=0b11NO=4)

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Step 1: Enable and configure clock sources

• Step 1D
o PLLCON[8:0] is set to 48 (i.e.,
FB_DV=48NF=48+2=50)
o PLLCON[13:9] is set to 1 (i.e.,
IN_DV=1NR=1+2=3)
o PLLCON[15:14] is set to 3 (i.e.,
OUT_DV=0b11NO=4)

• PLLCON[15:0] is set to
0b1100_0010_0011_0000 or 0xC230

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Step 1: Enable and configure clock sources

• Step 1D – Put the calculated register

value: CLK->PLLCON &= (~(0xFFFF << 0));

a. Clear the previous value if any

b. Set new value 0xC230

CLK->PLLCON |= 0xC230; //

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Step 1: Enable and configure clock sources

• Step 1E - To enable PLLOUT output:

CLK->PLLCON &= (~(1<<18));
a. PLLCON[18] is clear to 0

b. Wait for the PLL signal to stable –

this is the end of step 1
#define PLL_STATUS 1<<2

while(!(CLK->CLKSTATUS & PLL_STATUS));

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Step 2

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Step 2: Select the clock sources

• Step 2A – Allow the clock calculated

earlier flowing to the CPU - PLLOUT CLK->CLKSEL0 &= (~(0x07<<0));
must be selected for CPU

a. Clear value if any

b. CLKSEL0[2:0] is set to 0b010 CLK->CLKSEL0 |= 0b010;

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Step 2: Select the clock sources

• Step 2B – Power Down Mode Set

a. PWRCON[7] is 0b0. This is a

default/reset value -> no change in
the code.

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Step 2: Select the clock sources

• Step 2C – Check if we need to divide

the clock frequency further CLK->CLKDIV &= (~(0x0F<<0));

a. Since we got 50MHz, so here we will

not use the clock frequency divider
anymore

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Step 3 - Lock protected registers

• We will lock registers once we complete.

SYS_LockReg(); // Lock protected registers

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Full Program

Upload on Canvas

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Test the Clock Configuration

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Toggle a GPIO pin to confirm frequency

Be discussed in Tutorial 3

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Measurement

• The blinking frequency is 2.7 MHz

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Review Questions

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Tutorial Question 1

• Question 1: With the current clock configuration code, what is the clock source
and clock frequency of the MCU according to the Manual?

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Tutorial Question 2

• Question 2: What is the output signal frequency generated at GPIO port C pin
12 (i.e., the LED5’s flashing frequency) from the measurement?

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Tutorial Question 3

• Question 3: Study the manual and lecture, then modify the current embedded
software program to decrease CPU clock frequency by 50% compared to the
existing code. Build and load the new program to the board. Then, confirm the
flashing frequency of the GPC12 (LED5). Explain your changes and include the
snapshot from the measurement equipment.

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Tutorial Question 4

• Question 4: Study the manual and lecture, then modify the current embedded
software program to change the MCU clock frequency to 36 MHz (PLL should
be used as the CPU’s clock source). Build and load the new program to the
board. Then, confirm the flashing frequency of the GPC12 (LED5). Explain your
changes and include the snapshot from the measurement equipment.

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Steps for configuring MCU clock

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Summary - NUC140 MCU clock configuration (2)

•IMPORTANT NOTES:
o Always include code to check status of those clock sources after
enabling them.
o There are several options to tweak clock frequency to our
application’s needs (via CLKDIV and PLLCON).
o If a register (or one bit or groups of bits of that register) is write-
protected, it needs to be unlocked (by your software program)
before being written to (and locked after the register access is
completed to avoid further unwanted changes to them).

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—
Thank you

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Note

• Check solutions from Tutorial 2 Sample Solution.

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