CSE 243: Introduction to Computer Architecture

and Hardware/Software Interface

Topics covered:
CPU Architecture
 Multiple-bus organization

 Simple single-bus structure:

 Results in long control sequences, because only one data
item can be transferred over the bus in a clock cycle.
 Most commercial processors provide multiple internal
paths to enable several transfers to take place in
parallel.
 Multiple-bus organization.

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 Multiple bus organization (contd..)
Incrementer
Bus A Bus B Bus C

PC

Register
file

Constant
MUX A
4

ALU R

Instruction
decoder

IR

MDR Memory data lines

MAR Memory address lines

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 Multiple bus organization (contd..)

 Three-bus organization to connect the registers and the

ALU of a processor.
 All general-purpose registers are combined into a single
block called register file.
 Register file has three ports.
 Two outputs ports connected to buses A and B, allowing
the contents of two different registers to be accessed
simultaneously, and placed on buses A and B.
 Third input port allows the data on bus C to be loaded into
a third register during the same clock cycle.
 Inputs to the ALU and outputs from the ALU:
 Buses A and B are used to transfer the source operands to
the A and B inputs of the ALU.
 Result is transferred to the destination over bus C.

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 Multiple bus organization (contd..)

 ALU can also pass one of its two input operands

unmodified if needed:
 Control signals for such an operation are R=A or R=B.
 Three bus arrangement obviates the need for Registers
Y and Z in the single bus organization.
 Incrementer unit:
 Used to increment the PC by 4.
 Source for the constant 4 at the ALU multiplexer can be
used to increment other addresses such as the memory
addresses in multiple load/store instructions.

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Multiple bus organization (contd..)

Three operand instruction: ADD R4, R5, R6

Step Action

1 PCout, R=B, MAR in, Read, IncPC

2 WMFC ,MDR in
3 MDRoutB, R=B, IR in
4 R4outA, R5outB, SelectA, Add, R6in, End

1. Pass the contents of the PC through ALU and load it into MAR.
Increment PC.
2. Wait for MFC.
3. Load the data received into MAR and transfer to IR.
4. Execution of the instruction is the last step.

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 Control unit

 To execute instructions the processor must generate

the necessary control signals in proper sequence.
 Hardwired control:
 Control unit is designed as a finite state machine.
 Inflexible but fast.
 Appropriate for simpler machines (e.g. RISC machines)

 Microprogrammed control:
 Control path is designed hierarchically using principles
identical to the CPU design.
 Flexible, but slow.
 Appropriate for complex machines (e.g. CISC machines)

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 Hardwired control

Step Action Add (R3)R1

1 PCout , MAR in ,Read,Select4,Add, Zin

2 Zout , PC in , Y in , WMF C
3 MDRout , IR in
4 R3out , MAR in ,Read
5 R1out , Y in , WMF C
6 MDRout ,SelectY,Add, Zin
7 Zout , R1in , End

•Each step in this sequence is completed in one clock cycle.

•A counter may be used to keep track of the control steps.
•Each state or count, of this counter corresponds to one control step.

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 Hardwired control (contd..)

 Required control signals are determined by the

following information:
 Contents of the control step counter.
• Determines which step in the sequence.
 Contents of the instruction register.

• Determines the actual instruction

 Contents of the condition code flags.

• Used for example in a BRANCH instruction.

 External input signals such as MFC.

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 Hardwired control (contd..)
Control unit organization

CLK Control step

Clock counter

•Control unit consists of

External a decoder/encoder block to
inputs
accept the following inputs:
Decoder/
IR - Control step counter.
encoder
- Instruction Register.
Condition
codes - Condition codes
- External inputs.
•Generates control signals.

Control signals

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Hardwired control (contd..)
CLK
Clock Control step Reset
counter

Separate signal line for each step

Step decoder
Separate signal line for
Combines inputs to generate
each instruction T 1 T2 Tn
control signals
INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

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 Hardwired control (contd..)

Control signals such as Zin, PCout, ADD are generated by encoder block

Suppose if Zin is asserted:

- During T1 for all instructions.
- During T6 for ADD instruction.
- During T4 for unconditional BRANCH instruction
- ..............
BRANCH ADD

T4 T
6

T1

Z in T1  T6 . ADD  T4 .BRANCH  .....

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 Hardwired control (contd..)

 Control hardware can be viewed as a state machine:

 Changes state every clock cycle depending on the
contents of the instruction register, condition codes, and
external inputs.
 Outputs of the state machine are control signals:
 Sequence of control signals generated by the machine
is determined by wiring of logic elements, hence the
name “hardwired control”.
 Speed of operation is one of the advantages of
hardwired control is its speed of operation.
 Disadvantages include:
 Little flexibility.
 Limited complexity of the instruction set it can implement.

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 Microprogrammed control

 Hardwired control generates control signals using:

 A control step counter.
 Decoder/encode circuit.

 Microprogrammed control:
 Control signals are generated by a program similar to
machine language programs.

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 Microprogrammed control (contd..)

Control Word (CW) is a word whose individual bits represent various

control signals.
Control Signals:
Step Action PCout
PCin
MARin
1 PCout , MAR in ,Read,Select4,Add, Zin
Read
2 Zout , PC in , Yin , WMF C MDRout
3 MDRout , IR in IRin
Yin
4 R3out , MAR in ,Read SelectY
5 R1out , Yin , WMF C Select4
Add
6 MDRout ,SelectY,Add, Zin Zin
7 Zout , R1in , End Zout
R1out
At every step, some control signals R1in
are asserted (=1) and all others are 0. R3out
WMFC
End ...... 15
Microprogrammed control (contd..)

MDRout

WMFC
MARin

Select
PCout

R1out

R3out
Micro -

Read
PCin

R1in
Add

End
Z out
IRin
Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

•At every step,a Control Word needs to be generated.

•Every instruction will need a sequence of CWs for its execution.
•Sequence of CWs for an instruction is the microroutine for the instruction.
•Each CW in this microroutine is referred to as a microinstruction.

(SelectY is represented by Select=0, & Select4 by Select=1)

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 Microprogrammed control (contd..)

 Every instruction will have its own microroutine which is

made up of microinstructions.
 Microroutine for all instructions in the instruction set of
a computer are stored in a special memory called
Control Store.
 Recall that the Control Unit generates the control
signals:
 Sequentially reading the CWs of the corresponding
microroutine from the control store.

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 Microprogrammed control (contd..)
Basic organization of a microprogrammed control unit.

Starting •Microprogram counter (PC) is used to

IR address read CWs from control store sequentially.
generator •When a new instruction is loaded into IR,
Starting address generator generates the
starting address of the microroutine.
•This address is loaded into the PC.
PC is automatically incremented by the
Clock PC
clock, so successive microinstructions are
read from the control store.

Control
store CW

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 Microprogrammed control (contd..)

 Basic organization of the microprogrammed control unit

cannot check the status of condition codes or external
inputs to determine what should be the next
microinstruction.
 Recall that in the hardwired control, this was handled by
an appropriate logic function.
 How to handle this in microprogrammed control:
 Use conditional branch microinstructions.
 These microinstructions, in addition to the branch address
also specify which of the external inputs, condition codes
or possibly registers should be checked as a condition for
branching.

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 Microprogrammed control (contd..)

Address
Microinstruction

0 PCout , MAR in ,Read,Select4,Add, Zin

Fetch BRANCH<0 instruction,
1 Zout , PC in , Yin , WMFC
microroutine is at address 25.
2 MDRout , IRin
3 Branchtostartingaddress of appropriate microroutineBranch to address 25.
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 IfN=0, thenbranchtomicroinstruction0Test the N bit of the condition
26 Offset-field-of-IR codes
out ,SelectY,Add, Zin
If 0, go to 0 and get new instr.
27 Zout , PC in , End Else execute microinstruction
located at 26 and put the branch
target address into Register Z.
(Microinstruction at location 27).

Address 25 is the output of starting address generator and is loaded

into the microprogram counter (PC).

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 Microprogrammed control (contd..)
Control Unit with Conditional Branching in the Microprogram

External
inputs

Starting and
branch address Condition
IR codes
generator

Starting and branch

address generator instead
of starting address
Clock PC generator.

Control
store CW

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 Microprogrammed control (contd..)

 Starting and branch address generator accepts as inputs:

 Contents of the Instruction Register (as before).
 External inputs
 Condition codes
 Generates a new address and loads it into microprogram
counter (PC) when a microinstruction instructs it do so.
 PC is incremented every time a microinstruction is
fetched except:
 New instruction is loaded into IR, PC is loaded with the
starting address of the microroutine for that instruction.
 Branch instruction is encountered and branch condition is
satisfied, PC is loaded with the branch address.
 End instruction is encountered, PC is loaded with the
address of the first CW in the microroutine for the instruction
fetch cycle.

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