Synchronous Counters (Parallel

Counter)
 with respect to counter operation, synchronous
means that the counter is connected such that all
the Flip- Flops change at the same time
All flip-flops are clocked simultaneously by an
external clock.
Synchronous counters are faster than
asynchronous counters because of the
simultaneous clocking.
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 Asynchornous / Ripple counter
 The ripple counter is easy to build but there is a
limitation of to its highest operating frequency. Here
each flip-flop has a delay time and these delays are
additive so the propagation delay of the entire
counter is the sum of the individual delays. This
speed limitation can be overcome by the use of a
synchronous or parallel counter. Because here each
flip-flop is triggered by the clock and this makes
simultaneously transition in all the flip-flops. 2
MOD 4 Synchronous Counter

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MOD 8 Synchronous Counter

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MOD 10 Synchronous Counter

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 Cascading BCD Counters
 BCD counters are often used whenever
pulses are to be counted and the results
displayed in decimal.
 A single BCD counter counts from 0 to 9
and then recycles to 0.
 To count to a larger number than 9, we
should cascade a multiple of BCD counters

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 Cascading BCD Counters
 For example, to construct a BCD counter
operation that counts from 000 to 999 we
should proceed with the following design:

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 Cascading BCD Counters
1.Initially all counters are reset to 0.
2.Each input pulse advances the first counter once.
3.The 10th input pulse causes the counter to recycle, which advances the
second counter 1.
4.This continues until the second counter (10’s digit) recycles, which
advances the third counter 1.
5.The cycle repeat until 999 is reached and all three counters start again at
zero.

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 Procedure to Design Synchronous
Counters
 The procedure to design a synchronous
counter is listed here.

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 The excitation tables
 The excitation or characteristic table of SR
flip-flop, D flip-flip, JK flip-flop, and T
flip-flop are shown:
 Qt is denotes the output of the present state
and Qt+1 denotes the output of next state.

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The excitation tables

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 Example
 Design of a Synchronous Decade Counter Using JK Flip-
Flop.

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 Since there are ten states, four JK flip-flops are required. The truth
tables of present and next state for the decade counter are shown in
figure below. Using the excitation table of JK flip-flop and the
outputs of J and K are filled.

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 The Karnaugh maps of the output J0, K0, J1, K1, J2, K2, J3, and K3
are shown down respectively. The simplified results are at the bottom
of the Karnaugh maps.

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 Based on the results obtained from the Karnaugh maps,
the circuit design of synchronous decade counter is
shown below.

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 Example 2
Design of a Synchronous counter using SR latch which count
0, 2, 3, 6, 5,1,0
Solution:
 The counter will count 0, 2, 3, 6, 5, and 1 and repeat the
sequence.
 This counter requires three SR flip-flops for the design.
The truth table counter is shown . From the excitation table
of SR flip-flop shown , the logic of output S2, R2, S1, R1,
S0, and R0 are filled and shown in figure below.
 To fill the K-map , consider the present state and the
corresponding input you want to simplify.

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Karnaugh maps.

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 Examples
 Design a synchronous counter which count:
0,1,2,3,4,0

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 Solution
 STEP 1: determine the desired
number of bits (flip-flops) and the
desired counting sequence.
 We will use 3 JK Flip-flops to count
from 000 to 100 “i.e from 0 - 4”
 STEP 2: Draw the state transition
diagram showing all possible
states, including the undesired
states.
 The undesired states should go back to
000

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 Solution
 STEP 3: Use the state transition diagram
to set up a table that lists all PRESENT
states and their NEXT state.

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 Solution
 STEP 4: Add a column to the previous
table for each j and k input (Excitation
table)

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 Solution
 If we use JK flip-flops , we have to compute the
JK inputs for each flip-flop. Look at the present
and desired next state, and use the excitation
table shown below:

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 Solution
 STEP 5: Design the logic circuits to
generate the levels required at each j and
k input.
 Using Karnaugh Map “K-Map”

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Solution

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 Solution
 STEP 6: Implement the final expressions
 JA= C’ KA= 1
 JB= C’ A KB= C+A
 JC= B A KC= 1

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 Example 2
 Implement The Same Counter using D Flip-
flops.

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Example 2

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Example 3

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 Example 3
 Design a counter with the count sequence
shown in the state diagram of the following
figure . Use J-K flip-flops.

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 Solution
 Step 1: The state diagram is as shown. Although there are
only four states, a 3-bit
 counter is required to implement this sequence because
the maximum binary count is seven. Since the required
sequence dues not include all the possible binary states,
the invalid states (0, 3,4, and 6) can be treated as "don't
cares" in the design. However, if the counter get into an
invalid state, you must make sure that it goes back to a
valid state.
 Step 2: The next-state table is developed from the state
diagram and is given in the following table.
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Step 3: The transition table for the J-K flip-flop is repeated in

Step 4: The J and K inputs are plotted on the present-state

Karnaugh maps in Figure. Also "don't cares" can be placed
in the cells corresponding to the invalid states of 000, 011,
100, and 110, as indicated by the red Xs.
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Step 5: Group the 1 s, taking advantage of as many of the "don't
care" states as possible for maximum simplification. Notice that
when all cells in a map are grouped, the expression is simply
equal to I. The expression for each J and K input taken from
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the
maps is as follows:
Step 6: The implementation of the counter is shown:

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 Example 4
 Design a synchronous counter to count the
gray code sequence as is illustrated:

Step 1: State Diagram

The first step in the design of a counter is to create a state
diagram. A state diagram shows the progression of states
through which the counter advances when it is clocked. As an
example, is a state diagram for a basic 3-bit Gray code counter.
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 This particular circuit has no inputs other than the clock
and no outputs other than the outputs taken off each
flip-flop in the counter. You may wish to review the
coverage of the Gray code in at this time.
 Step 2: Next-State Table
 Once the sequential circuit is defined by a state
diagram. the second step is to derive a next- state table,
which lists each state of the counter (present state)
along with the corresponding next state. The next state
is the state that the counter goes to from its present State
upon application of a clock pulse The next-state table is
derived from the state diagram and is shown in Table
for the 3-bit Gray code counter. Qo is the least
significant bit. 37
 Present State Next State
 Next state table: Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
Output Flip-Flop
0 1 1 0 1 0
Transitions Inputs 0 1 0 1 1 0
QN Q N+1 J K 1 1 0 1 1 1
1 1 1 1 0 1
0 0 0 X 1 0 1 1 0 0
0 1 1 X 1 0 0 0 0 0
1 0 X 1
1 1 X 0

Step 3: Flip-Flop Transition Table

Table above is a transition table for the J-K flip-flop. All
possible output transitions are listed by showing the Q output
of the flip-flop going from present states to next states. QN is
the present state of the flip-flop (before d clock pulse) and
QN + I is the next state (after a clock pulse). For each output
transition. the 1 and K inputs that will cause the transition to
occur are listed. An X indicates a "don't care" (the input can
be either a I or a 0).
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To design the counter, the transition table is applied to each of
the flip-flops in the
counter, based on the next-state table (Table 8-7). For
example, for the present state 000, Qo goes from a present
state of 0 to a next state of 1. To make this happen, 10 must
be a I and you don't care what Ko is (jo = I, Ko = X), as you
can see in the transition table. Next, QI is 0 in the present
state and remains a 0 in the next state. For this transition, 1 1
= 0 and K, = X. Finally, Q2 is 0 in the present state and
remains a 0 in the next state.
Therefore, 1 2 = 0 and K 2 = X. This analysis is repeated for
each present state in Table

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 Step 4: Karnaugh Maps
 Karnaugh maps can be used to determine the logic required
for the 1 and K inputs of each flip-flop in the counter. There
is a Karnaugh map for the 1 input and a Kamaugh map for
the K input of each flip-flop. In this design procedure, each
cell in a Kamaugh map represents one of the present states
in the counter sequence listed in Table 8-7.
 From the 1 and K states in the transition table (Table 8-8) a
1,0, or X is entered into each present state cell on the maps
depending on the transition of the Q output for a particular
flip- flop. To illustrate this procedure, two sample entries
are shown for the 10 and the Ko inputs to the least
significant flip-flop (Qo)
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  Step 5: logic Expressions for Flip-Flop Inputs
 From the Karnaugh maps you obtain the
following expressions for the 1 and K inputs of
each flip-flop:

Step 6: Counter Implementation

The final step is to implement the combinational logic from
the expressions for the 1 and K inputs and connect the flip-
flops to form the complete 3-bit Gray code counter as 43
shown:
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 Shift Register Counters
 Ring Counter (circulating shift register)
 Last FF shifts its value to first FF
 Uses D-type FFs (JK FFs can also be used)
 Must start with only one FF in the 1 state and all others in
the 0 state.
 Ring Counter: MOD-4, 4 distinct states
 Does not count in normally binary sequence, but it is still a counter
 Each FF output waveform frequency equals one- fourth of the clock frequency

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 Johnson’s Counter
 Johnson counter (Twisted ring counter)
 Same as ring counter but the inverted output of the
last FF is connected to input of the first FF
 MOD is twice the number of FF
(Example is MOD 6)
 Does not count normal binary sequence
 Six distinct states: 000, 100, 110, 111, 011, 001
before it repeats the sequence
 Waveform of each FF is a square wave (50% duty
cycle) at 1/6 the frequency of the clock

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 Counter Applications
Car Parking Control
 The counter controls the gate activation for
lowering and rising the gate depending on
the number of parked cars
 Each car enters the parking will ascend the
counter by one “up”
 Each car exists the parking will descend the
counter by one “down”

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 Car Parking Control
Display
Entrance Sensor

Available / Full
UP
Interface
Down
Lower/Rise
Exit Sensor

Gate Activation

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 ASSIGNEMENT/10

 Design a MOD-9 Asynchronous counter a

nd synchronous counter using JK flip-flop
negative edge triggered

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