Simulation Mismatch

ATPG
• is the process of generating the test vectors
for the particular test mode to check the
manufacturing defects, which is further used
by simulation tools for validation.
• ATPG is performed on scan inserted design
and the SPF generated through scan insertion.
Simulation is the later stage after ATPG, for
the validation of the patterns generated in
different formats.
• Simulation/Pattern validation plays a vital role in DFT, in
order to examine the vectors generated by the ATPG tool.
• Once the design is ready with scan inserted netlist, test
vectors will be generated and the same vectors will be used
for simulation.
• If any Error or severe warnings occurs at ATPG/vector
generation stage, it can either be solved at the same stage,
else we need to jump to SCAN stage for the required
changes which helps to clean ATPG issues.
• If the pattern simulation failure occurs, we need to analyze
the failure and need to do necessary changes in ATPG stage
like spf modification to clean up the simulation failures.
 Simulation Mismatches During
Test-Pattern Verification
• Test-pattern verification is based on the
device timing information to ensure that the
patterns can be applied to the real circuits.
• If any mismatches occur between the timing-
based simulation results and the expected
results, the test patterns must be corrected.
• If test patterns aren't corrected, good devices
would be rejected during the manufacturing
test process.
 The most common simulation
mismatches are as follows:
Timing Issues:
• Timing-related issues generally occur because of
clock skew between the successive scan cells in
the design.
• If the propagation delay at the data path
between two successive scan cells is less than the
propagation delay at the clock path, clock skew
occurs.
• Conceptually, it would be ideal to have only one
scan clock. But this actually creates more clock-
skew problems, due to the multiplexing together
of asynchronous clocks.
 Multiple Clock Domains
• A clock domain is a grouping of sequential
elements sharing a single clock in the design
block. If two design blocks share the same clock,
then there must be clock skew between the two
blocks. Clock skew is important because although
it's easy to meet the setup timing requirement, it
will create a problem with hold-time violations
during scan testing. To avoid the hold-time
problems during scan testing, add buffers in the
clock path
 Bidirectional I/Os
• Handle bidirectional I/Os with care during
test-pattern verification. The ATPG tool can
generate patterns when the bidirectional I/Os
change direction as a result of the capture
clock. Testers generally don't support this
function. So, you should force the ATPG tool
to generate scan patterns that don't change
the direction of the bidirectional IOs during
the capture cycle.
For Non sequential elementx
For scan elements
 SPF
• SPF stands for STIL(Standard test interface
language) protocol file generated after the scan
insertion stage, which consists of all the
necessary and basic scan information.
• In general words, SPF portrays the information of
scan structure, scan chain, initial state value for
all the signals for particular test mode and
furthermore.
• All the above-defined information in SPF is
needed to guide the ATPG tool for DRC checks
and pattern formatting.
• SPF is assigned at the run_drc stage to verify
the compatibility of scan inserted netlist with
the SPF, it further determines how the scan
structure can be used to generate patterns
and fault simulations.
 SPF Skeleton
1.Signals-It is the first section of SPF containing definition
of all the signals with their type(In, Out, InOut etc)
2. Signal Grouping -The grouping signals further used to
provide constraint value at different procedures.
all_in” “all_out”, “all_ports”, “all_bidi”, “_pi”, “_po”,
“_si”, “_so”
3.Scan Structure-This section includes the scan chain
information like scan chain name, Scan_in, scan_out
and scan_enable pin and also the clock used by that
particular chain.
 4.Timing
• Waveform table is defined in this section which
includes the description of the different values
provided to different signals like clock period
definition, reset value, test mode value etc.
• Waveform table is defined for all the different
procedures which are required for different use :
• Default_WFT
• Multiclock_capture_WFT
• Allclock_capture_WFT
• Allclock_launch_WFT
• Allclock_launch_capture_WFT
• “Default_WFT” is used for loading and unloading
of the vectors, or we can say for shifting purpose.
• Among all the above-defined WFT,
multiclock_capture is the default capture
procedure for all the fault models, always used
by the Stuck-at fault model.
• “allclock_*_WFT” is used for at-speed testing,
you can the clock frequency based on the
requirement for the capture procedure.
 5.Procedure
• Procedures are defined for the capture cycle
of stuck-at and at-speed faults like
Multiclock_capture, allclock_capture,
allclock_launch, allclock_launch_capture
procedures.
Example of one capture procedure,
and how its structure looks like:
 MacroDefs
• This division includes the test setup part
through which we can initialize the instruction
and data bit registers at the TAP/top level.
• Also, the test setup is required to provide the
values to the signals before the pattern
generation starts for the scan mode to bring
chip in its known state like functional mode,
test mode, MBIST mode, etc.
Possible Mismatches Causes