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EEE3105 ch02

Chapter 02 covers Boolean Algebra and Logic Simplification, detailing logic operations, Boolean variables, and basic operations like AND, OR, and NOT. It explains the use of truth tables, timing diagrams, and K-maps for analyzing and simplifying logic circuits. The chapter also discusses the implications of logic simplification in terms of hardware efficiency and potential timing issues.

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Wing Wing Wong
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0% found this document useful (0 votes)
17 views58 pages

EEE3105 ch02

Chapter 02 covers Boolean Algebra and Logic Simplification, detailing logic operations, Boolean variables, and basic operations like AND, OR, and NOT. It explains the use of truth tables, timing diagrams, and K-maps for analyzing and simplifying logic circuits. The chapter also discusses the implications of logic simplification in terms of hardware efficiency and potential timing issues.

Uploaded by

Wing Wing Wong
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Digital Electronics and

Microprocessor
Fundamentals

Chapter 02 : Boolean Algebra &


Logic Simplification

02/04/2025 (C) VTC 2012 p.1


Logic Operations
 Symbol
 Active-high

 Active-low

 Bubble – a small circle indicating logic inversion on a

circuit symbol
 Boolean Algebra
 Logic Equations
 Truth Table
 Timing Diagram

02/04/2025 (C) VTC 2012 p.2


Boolean Algebra
 Boolean Variables (or Logic Variables)
 value can be 0 or 1 (True or False)

 In digital systems, logic-0 and logic-1 are

represented as a voltage (or voltage range)


 Each variable is assigned a name beginning with a

letter in most examples


 E.g. P, ALARM, O1,O2, X3O, …

 Boolean Algebra
 a mathematical process for analyzing and simplifying

Boolean expressions to help analyze a logic circuit


and express its operation mathematically
 deals with Boolean variables only

02/04/2025 (C) VTC 2012 p.3


Boolean Algebra
 Basic Boolean Operations (or Logic Operations)
 AND

 OR

 NOT (or Logic Complement, Inversion)

 Other Boolean operations


 NAND

 NOR

 Exclusive-OR

 Exclusive-NOR

02/04/2025 (C) VTC 2012 p.4


Boolean Algebra
 Boolean Function
 Boolean Operations

 Boolean Variables

 Logic Gate
 an electrical circuit that performs a Boolean algebraic

function

02/04/2025 (C) VTC 2012 p.5


Logic Functions
NOT AND OR

F=A F=AB F=A+B


A A
A F C C
B B

02/04/2025 (C) VTC 2012 p.6


Logic Functions
NAND NOR Exclusive-OR Exclusive-NOR

F=AB F=A+B F=AÅ B F=AÅ B

A A A A
F F F F
B B B B

02/04/2025 (C) VTC 2012 p.7


Logic Functions
 Exclusive-OR

F A  B AB  A B
 Exclusive-NOR

F A  B AB  A B

02/04/2025 (C) VTC 2012 p.8


Theorems of Boolean Algebra
 Boolean Theorems
 to simplify logic expressions and logic circuits

02/04/2025 (C) VTC 2012 p.9


Theorems of Boolean Algebra
 De Morgan’s Theorems
XY X  Y

 May involve more than 2 or more variables, so generally

ABCD...N A  B  C  D  ...  N

A  B  C  ...  N A.B.C...N

02/04/2025 (C) VTC 2012 p.10


Theorems of Boolean Algebra - Example
 Simplify X + X’Y
From Law #12,
X + X’Y = (X + X’)(X + Y) = (1)(X + Y) = X + Y

 Simplify (A’ + B + C + D)’ + AB’C’D

(A’ + B + C + D)’ + AB’C’D


= A’’ B’ C’ D’ + AB’C’D
= AB’C’D’ + AB’C’D
= AB’C’ (D’ + D)
= AB’C’

02/04/2025 (C) VTC 2012 p.11


Theorems of Boolean Algebra - Example
 Simplify F = A’BC + AB’C + ABC + BC’
F = A’BC + AB’C + ABC + BC’
= A’BC + ABC + AB’C + BC’
= (A’ + A) BC + AB’C + BC’
= BC + BC’ + AB’C
= B + B’AC
= B + AC
 Simplify W = Y’(X + Z) + Z(X’ + Y) + XZ
W = Y’(X + Z) + Z(X’ + Y) + XZ
= Y’X + Y’Z + ZX’ + ZY + XZ
= Y’X + Z(Y’ + X’ + Y + X)
= Y’X + Z
02/04/2025 (C) VTC 2012 p.12
Theorems of Boolean Algebra - Example
 Classwork Exercise:

Simplify F = A’C + A’B + AB’C + BC

F = A’C + A’B + AB’C + BC


= A’B + (A’C + AB’C + BC)
= A’B + C(A’ + AB’ + B)
= A’B + C[A’ + (AB’ + B)]
= A’B + C[A’ + (A + B)]
= A’B + C[(A’ + A) + B]
= A’B + C(1 + B)
= A’B + C

02/04/2025 (C) VTC 2012 p.13


Truth Table
 A tabular form to describe how the output of a logic
circuit depends on the logic levels present at the circuit’s
input
 2n rows for a n-input logic function

02/04/2025 (C) VTC 2012 p.14


Truth Table
 Draw a truth table to prove X  XY X  Y

02/04/2025 (C) VTC 2012 p.15


Truth Table
 Draw a truth table for the logic function 
F AB BC  A 

02/04/2025 (C) VTC 2012 p.16


Truth Table
 Classwork Exercise:

Draw a truth table to prove

A + (B C) = (A + B)(A + C)

02/04/2025 (C) VTC 2012 p.17


Universal Gates
 Determine the output F for each case. Comment on the
results obtained.
A
F
B
A
F
F= B

F=
A F

A
F=
F

F=
02/04/2025 (C) VTC 2012 p.18
Universal Gates
 NOR gates can also be used to implement NOT, AND
and OR gates

 Classwork Exercise:

Draw logic diagrams and write Boolean equations to


show the implementation of NOT, AND and OR gates
using only NOR gates.

02/04/2025 (C) VTC 2012 p.19


Universal Gates
 Any of the Boolean operations can be implemented
using only NAND / NOR gates

 Any logic circuit can be implemented using only NAND /


NOR gates

 Useful in logic circuit design to keep using a single type


of fixed-function IC

02/04/2025 (C) VTC 2012 p.20


Universal Gates – Examples
 Example:

Use 2-input NAND gates to implement the following logic


function:

F = A(B + C)

Draw a logic diagram to illustrate your answer.

Repeat the same example but using 2-input NOR gates.

02/04/2025 (C) VTC 2012 p.21


Timing Diagrams
 A graphical view showing the signal values over time
 A graph of voltage vs time

 Useful to show
 how digital signals change with time

 the timing relationship between 2 or more logic signals

in the same circuit or system

 Practical measurement will display one or more signals


on an Oscilloscope or Logic Analyzer for comparison

02/04/2025 (C) VTC 2012 p.22


Timing Diagrams
 Example:

The timing diagram in Fig 1 shows the input and output


waveforms of a logic gate. Identify the logic gate.

1
A
0
1
B
0
1
F
0
time / t
Fig 1
02/04/2025 (C) VTC 2012 p.23
Examples
 Example:

Simplify the logic circuit in Fig 1.

A
A A  BC

B BC
C A
F
B
Fig 1

02/04/2025 (C) VTC 2012 p.24


Examples
 Example:

Using 2-input NAND gates only, implement the following


Boolean functions:

Y = AB + CD

02/04/2025 (C) VTC 2012 p.25


Truth Table & Boolean Function
 Consider the truth table for an AND gate, we can see
that F = AB
 The truth table tells us that F = 1 only when input A

AND B are both equal

02/04/2025 (C) VTC 2012 p.26


Truth Table & Boolean Function
 For OR gate, the truth table tells us that when
 A = 0, B = 1 (i.e. A’B) then F = 1, or
 A = 1, B = 0 (i.e. AB’) then F = 1, or
 A = 1, B = 1 (i.e. AB) then F = 1
 So, in the form of Boolean expression
 F = A’B + AB’ + AB

= A’B + A(B’ + B)
= A’B + A
=A+B

02/04/2025 (C) VTC 2012 p.27


Truth Table & Boolean Function
 Determine a Boolean function from a truth table
 first, draw a truth table for the various input

combinations and the corresponding output


 pick up these input combinations which produces

logic-1 output to form a Boolean equation


 then, simplify the Boolean function using the various

‘Laws’ of Boolean Algebra

02/04/2025 (C) VTC 2012 p.28


Truth Table & Boolean Function
 Example:

Find the Boolean function for each of the following truth


tables:

02/04/2025 (C) VTC 2012 p.29


Truth Table & Boolean Function

 Example:

Determine the Boolean function F.

02/04/2025 (C) VTC 2012 p.30


SOP : Minterms
The following shows all minterms in a 3-input truth table

02/04/2025 (C) VTC 2012 p.31


SOP : Minterms
 Sum-of-Product (SOP) form
 PRODUCT term; e.g. A’B’C’, A’B’C, …, ABC’, ABC

 pick up all the input combinations which produces

logic-1 output
 Each PRODUCT term in a SOP form is called a

‘minterm’

 Example: Refer the example in p. 31

F = A’BC + AB’C’ + AB’C + ABC’ + ABC  SOP Form


= (m3, m4, m5, m6, m7)
= m(3, 4, 5, 6, 7) <- Canonical
Form
02/04/2025 (C) VTC 2012 p.32
Logic Simplification
 Hardware implications
 Reduce circuit size (e.g. area of a silicon chip, no. of

components)
 reduce power consumption
 reduce fabrication costs
 reduce PCB size
 shorten propagation delay => increase in speed
 improve circuit testability & reliability

 Drawback of Simplification
 Timing problems

02/04/2025 (C) VTC 2012 p.33


Digital Electronics and
Microcomputer Fundamentals

Chapter 02 K-Map

02/04/2025 (C) VTC 2012 p.34


K-Map & Boolean Function
 K-Map (or Karnaugh Map)
 A map which shows the relation between the input and

output of a logic expression


 Similar to a truth table

 Consists of one square (called a ‘cell’) for each

possible minterm in a logic function


 2 variables => 4 cells

 3 variables => 8 cells

 4 variables => 16 cells

 K-Map up to 4 variables will be tested in ENG3105

02/04/2025 (C) VTC 2012 p.35


K-Map & Boolean Function

a cell
LSB LSB
BC minterm
BC
MSB BC BC BC BC MSB BC BC BC BC
A 00 01 11 10
A 00 01 11 10
minterm no.
A 0 m0 m1 m3 m2 A 0 A’B’C’ A’B’C A’BC A’BC’
0 1 3 2 0 1 3 2

A 1 m4 m5 m7 m6 A 1 A’BC AB’C ABC ABC’


4 5 7 6 4 5 7 6

3-variable K-Map 3-variable K-Map

02/04/2025 (C) VTC 2012 p.36


K-Map & Boolean Function

a cell
LSB LSB
CD minterm
CD
MSB CD CD CD CD MSB CD CD CD CD
AB 00 01 11 10
AB 00 01 11 10
minterm no.
A B 00 m0 m1 m3 m2 A B 00 A’B’C’D’ A’B’C’D A’B’CD A’B’CD’
0 1 3 2 0 1 3 2

A B 01 m4 m5 m7 m6 A B 01 A’BC’D’ A’BC’D A’BCD A’BCD’


4 5 7 6 4 5 7 6

A B 11 m12 m13 m15 m14 A B 11 ABC’D’ ABC’D ABCD ABCD’


12 13 15 14 12 13 15 14

A B 10 m8 m9 m11 m10 A B 10 AB’C’D’ AB’C’D AB’CD AB’CD’


8 9 11 10 8 9 11 10

4-variable K-Map 4-variable K-Map

02/04/2025 (C) VTC 2012 p.37


K-Map & Boolean Function
 Notice that the minterm nos. are not in sequential order
 The key ideas is to make the minterms in adjacent

cells different by one variable changing


 Grouping of cells for simplification

02/04/2025 (C) VTC 2012 p.38


K-Map & Boolean Function
 To plot a logic function into a K-Map
 put a ‘1’ in each cell corresponding to a minterm that is

included in the logic function


 put a ‘0’ in those cells not included in the logic function

02/04/2025 (C) VTC 2012 p.39


K-Map - Example
 Draw the K-map for the following Boolean function:

F = A’B’C’D’ + AB’C’D’ + A’B’C’D + A’BC’D + AB’C’D +


A’B’CD + A’BCD + ABCD + AB’CD + A’B’CD’ +
A’BCD’ + AB’CD’

Solution:

F = Sm(0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 15)


= PM(4,12,13,14)

Note: F’ = Sm(4, 12, 13, 14)

02/04/2025 (C) VTC 2012 p.40


K-Map - Example
LSB
CD
MSB CD CD CD CD
AB 00 01 11 10

A B 00 1 1 1 1
0 1 3 2

A B 01 0 1 1 1
4 5 7 6

A B 11 0 0 1 0
12 13 15 14

A B 10 1 1 1 1
8 9 11 10

02/04/2025 (C) VTC 2012 p.41


K-Map - Example
LSB
CD
MSB CD CD CD CD
AB 00 01 11 10

A B 00 1 1 1 1
0 1 3 2

A B 01 0 1 1 1
4 5 7 6

A B 11 0 0 1 0
12 13 15 14

A B 10 1 1 1 1
8 9 11 10

F = m(0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 15)


02/04/2025 (C) VTC 2012 p.42
K-Map & Simplification
 By grouping adjacent cells of same logic state together
can simplify the logic expression
 Rules of Grouping:
 Always use a group size of 2, 4, 8 or 2n adjacent cells

 All 1’s should be picked up, don’t leave any ‘1’

unattended
 Each group – as large as possible

 As smaller number of group as possible

 Groups can overlap

 Don’t create sub-group: a small group within a larger

group

02/04/2025 (C) VTC 2012 p.43


K-Map & Simplification – Some grouping examples
 Find out all possible groupings and derive the simplified
logic function.
LSB
CD
MSB CD CD CD CD
AB 00 01 11 10

A B 00 1 1 1 1
0 1 3 2

A B 01 0 1 1 1
4 5 7 6

A B 11 0 0 1 0
12 13 15 14

A B 10 1 1 1 1
8 9 11 10

F = m(0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 15)


02/04/2025 (C) VTC 2012 p.44
K-Map & Simplification – Some grouping examples
 Example: Find out all possible groupings and derive the
equivalent logic function.

02/04/2025 (C) VTC 2012 p.45


K-Map & Simplification – Some grouping examples
 Example: Find out all possible groupings and derive the
equivalent logic function.

02/04/2025 (C) VTC 2012 p.46


K-Map & Simplification – Some grouping examples
 Example: Find out all possible groupings and derive the
equivalent logic function.

02/04/2025 (C) VTC 2012 p.47


K-Map & Simplification - Example
 The K-map of a logic function G is given as follows:
LSB
CD
MSB CD CD CD CD
AB 00 01 11 10

A B 00 1 1 0 1
0 1 3 2

A B 01 0 1 0 0
4 5 7 6

A B 11 0 0 0 0
12 13 15 14

A B 10 1 1 0 1
8 9 11 10

Find the simplified SOP form of G.

02/04/2025 (C) VTC 2012 p.48


Don’t Care Term
 In some practical situations, certain combinations of
inputs will not occur and so the corresponding outputs
are not important
 Hence, we don’t care the output to be marked ‘0’ or ‘1’

in a truth table
=> we mark it ‘X’ or ‘d’

 A don’t care term ‘X’ may be treated as ‘1’ or ‘0’; thus the
logic function and the actual circuit can be further
simplified

02/04/2025 (C) VTC 2012 p.49


K-Map & Simplification – Some grouping examples
 Example: Find out all possible groupings and derive the
equivalent logic function.
LSB
BC
MSB BC BC BC BC
A 00 01 11 10

A 0 0 0 X 0
0 1 3 2

A 1 0 1 X 1
4 5 7 6

02/04/2025 (C) VTC 2012 p.50


Don’t Care Term - Example
 The truth table of a logic function F is given in Fig 9.

Find the simplified SOP form of F by picking up only ‘1s’


in the K-Map.

Find the simplified SOP form of F by considering also the


don’t care terms in the K-Map

02/04/2025 (C) VTC 2012 p.51


Fig 9
02/04/2025 (C) VTC 2012 p.52
1 1 1 1

0 0 0 0

0 0 0 0

1 1 1 1

Fig 10 K-Map for the Truth Table in Fig 9

02/04/2025 (C) VTC 2012 p.53


Don’t Care Term - Example
 Draw the truth table to illustrate the behaviour of a 8421
BCD-to-Excess-3 Code Converter

MSB D8 E3 MSB

D4 8421 BCD-to- E2
Excess-3
D2 Code Comverter E1

LSB D1 E0 LSB

02/04/2025 (C) VTC 2012 p.54


02/04/2025 (C) VTC 2012 p.55
Don’t Care Term - Example
 How can you
 write the logic equation of each output with ‘don’t care’

terms, and
 simplify the logic equations ?

02/04/2025 (C) VTC 2012 p.56


02/04/2025 (C) VTC 2012 p.57
Q&A

End-of-Chapter 02

02/04/2025 (C) VTC 2012 p.58

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