23CSE213

Computer Organization and

Architecture
Instruction Set Architecture, Processor Architecture

Department of CSE
2024-25 Even semester
 Contents
• ARM processor
• Registers and operands
• Instruction formats

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 ARM processor LEG - Lessen Extrinsic Garrulity
• The words of a computer’s language are called instructions, and its vocabulary
is called an instruction set.
• ARM LEGv8 processor is a special version of ARM processor with the
following characteristics:
• Register file: LEGv8 has a 32 × 64-bit register file
• 64-bit data is called a “doubleword”
• 0 to 30 registers are 64-bit general purpose registers X0 to X30
• 31 register – XZR – initialized to zero always.
• 32-bit data called a “word”
• 31 x 32-bit general purpose sub-registers W0 to W30
In LEGv8, a "sub-register" refers to a 32-bit portion of a 64-bit register, specifically
the lower 32 bits.
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 Arithmetic Example
• C code:
f = (g + h) - (i + j);
• Compiled LEGv8 code:
ADD t0, g, h // temp t0 = g + h
ADD t1, i, j // temp t1 = i + j
SUB f, t0, t1 // f = t0 - t1

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 Arithmetic operations
• Add and subtract, three operands
• Two sources and one destination
ADD a, b, c // a gets b + c
• All arithmetic operations have this form
• Design Principle 1: Simplicity favours regularity
• Regularity makes implementation simpler
• Simplicity enables higher performance at lower cost
• Arithmetic instructions use register operands
• Design Principle 2: Smaller is faster
• c.f. main memory: millions of locations

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 LEGv8 Registers used as operands
• X0 – X7: procedure arguments/results
• X8: indirect result location register
• X9 – X15: temporaries
• X16 – X17 (IP0 – IP1): may be used by linker as a scratch register, other times as
temporary register
• X18: platform register for platform independent code; otherwise a temporary register
• X19 – X27: saved registers
• X28 (SP): stack pointer
• X29 (FP): frame pointer
• X30 (LR): link register (return address)
• XZR (register 31): the constant value 0

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 Register operand example
• C code:
f = (g + h) - (i + j);
• f, …, j in X19, X20, …, X23

• Compiled LEGv8 code:

ADD X9, X20, X21
ADD X10, X22, X23
SUB X19, X9, X10

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 Memory Operands and how to reach data?
• Main memory used for composite data
• Arrays, structures, dynamic data
• Memory - large, single-dimensional array, with
the address acting as the index to that array,
starting at 0.
• LEGv8 must include instructions that transfer
data between memory and registers. Such
instructions are called data transfer
Actual LEGv8 memory addresses and
instructions. contents of memory for those
• To access a word or doubleword in memory, the doublewords. Since LEGv8
instruction must supply the memory address. addresses
each byte, doubleword
addresses are multiples of 8:
there are 8 bytes in a
doubleword.
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 Transfer data
• The data transfer instruction that copies data from memory to a register is
traditionally called load.
• LDUR, standing for load register.

• LDUR X1, [X2 + offset]

• X1 = Memory [X2 + offset]

• Gets the data from location X2 + offset and stores in X1.

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 Memory Operand Example – Load and store
• C code:
A[12] = h + A[8];

• h in X21, base address of A in X22

• Compiled LEGv8 code: Index 8 requires offset of 64

LDUR X9,[X22,#64] // U for “unscaled” – Value of shift after multiplying with 8

ADD X9,X21,X9
STUR X9,[X22,#96]

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 Registers vs Memory
• Registers are faster to access than memory
• Operating on memory data requires loads and stores - More instructions to
run.
• Compiler must use registers for variables as much as possible
• Only spill to memory for less frequently used variables
• Registers Data in registers both considerably faster to
• Take less time to access access, less energy used and simpler to use.
• Have higher throughput than memory
• An ISA must have enough registers, and compilers must use registers
efficiently.

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 Immediate operand
• Case 1: Loading a constant from memory
AddrConstant4 is the offset to be added to X20, where constant 4 is stored.
Pick the constant from that location put into X9. Use X9 for addition.
LDUR X9, [X20, AddrConstant4]
ADD X22,X22,X9
• Case 2: Constant data specified in an instruction Analyze both
ADDI X22, X22, #4 cases

• Design Principle 3: Make the common case fast

• Small constants are common
• Immediate operand avoids a load instruction
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 Representing instructions
• Instructions are encoded in binary (series of high and low electronic Signals)
• Called machine code
• LEGv8 instructions
• Encoded as 32-bit instruction words
• Small number of formats encoding operation code (opcode), register numbers, …
• Regularity!
• Base 16
• Compact representation of bit strings
• 4 bits per hex digit
• Example: eca8 6420
• 1110 1100 1010 1000 0110 0100 0010 0000

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 Stored Program Computers - Overview
The BIG Picture • Instructions represented in binary, just
like data.
• Instructions and data stored in memory.
• Programs can operate on programs.
• e.g., compilers, linkers, …
• Binary compatibility allows compiled
programs to work on different
computers.
• Standardized ISAs

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 LEGv8 – Instruction Fields
• LEGv8 fields are given names :

• opcode: Basic operation of the instruction, and this abbreviation is its

traditional name.
• Rm: The second register source operand.
• shamt: Shift amount. (Section 2.6 explains shift instructions and this term; it
will not be used until then, and hence the field contains zero in this section.)
• Rn: The first register source operand.
• Rd: The register destination operand. It gets the result of the operation

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 Considerations
• When an instruction needs longer fields:

• Case: the load register instruction must specify two registers and a constant.
• If the address were to use one of the 5-bit fields in the format above, the
largest constant within the load register instruction would be limited to only
25−1 or 31.
• Array size is limited.
• Conflict between the desire to keep all instructions the same length and the
desire to have a single instruction format.

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 Instruction formats
• Design Principle 4: Good design demands good compromises.
• This concept justifies the need for distinct instruction formats for different
kinds of instructions.

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 LEGv8 R-format Instructions

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 LEG8 I-format Instructions

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 LEGv8 D-format Instructions
opcode address op2 Rn Rt

11 bits 9 bits 2 bits 5 bits 5 bits

Load/store instructions
Rn: base register
address: constant offset from contents of base register (9
bits address range)
Rt: destination (load) or source (store) register number

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 LEGv8 Branch Instructions

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 Unconditional branch

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 Consolidated Instructions

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 Opcode for instructions

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 Scaled and Unscaled offset – An important point to note
• Load Register – Unscaled : X20 – has address of A[0]
• Work to do: X9 = A[2]
• LDUR X9, [X20,#16]
Locatio A[0 A[1] A[2] A[3] A[4]
n ]
Content 6 7 4 8 8
• Load Register – Scaled
• LDR X9, [X20, #2]

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 Example 1
ADD X9, X20, X21 – R
format
ADD X10, X22, X23 – R
format
SUB X19, X9, X10 – R
format

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 Example 1
• ADD X9, X20, X21
ADD X9, X20,
opcode: ADD → 10001011000 X21
Rm: X21 → 10101 ADD X10, X22,
shamt: 000000 X23
Rn: X20 → 10100 SUB X19, X9, X10
Rd: X9 → 01001
10001011000 10101 000000 10100 01001
8B150289

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 Example 1
• ADD X10, X22, X23
ADD X9, X20, X21
opcode: ADD → 10001011000 ADD X10, X22,
Rm: X23 → 10111 X23
shamt: 000000 SUB X19, X9, X10
Rn: X22 → 10110
Rd: X10 → 01010

10001011000 10111 000000 10110 01010

8B1702AA

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 Example 1
• SUB X19, X9, X10
ADD X9, X20, X21
ADD X10, X22,
opcode: SUB → 11001011000
X23
Rm: X10 → 01010 SUB X19, X9, X10
shamt: 000000
Rn: X9 → 01001
Rd: X19 → 10011
11001011000 01010 000000 01001 10011
CB0A1253

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 Example 1
• Final Hexadecimal Codes: ADD X9, X20, X21
• ADD X9, X20, X21 → 8B150289 ADD X10, X22,
• ADD X10, X22, X23 → 8B1702AA X23
• SUB X19, X9, X10 → CB0A1253 SUB X19, X9, X10

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 Example 2 LDUR X9,[X22,#64] – D format
ADD X9,X21,X9 – R format
• LDUR X9, [X22, #64] STUR X9,[X22,#96] – D format

Opcode: LDUR is a D-format instruction. opcode 11111000010.

Rn (Base Register): X22 → 10110.
Rt (Destination Register): X9 → 01001.
Address Offset: #64 → 64 in binary → 00000100000 (9 bits).
Combining the fields:

11111000010 00000100000 10110 01001

hexadecimal: F8402853.
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 Example 2 LDUR X9,[X22,#64]
ADD X9,X21,X9
• ADD X9, X21, X9 STUR X9,[X22,#96]

Opcode: ADD is an R-format instruction. opcode 10001011000.

Rm (Second Operand): X9 → 01001.
shamt (Shift Amount): 000000 (6 bits, default).
Rn (First Operand): X21 → 10101.
Rd (Destination Register): X9 → 01001.

10001011000 01001 000000 10101 01001

hexadecimal: 8B090289.
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 Example 2 LDUR X9,[X22,#64]
ADD X9,X21,X9
• STUR X9, [X22, #96] STUR X9,[X22,#96]

Opcode: STUR is a D-format instruction. opcode 11111000000.

Rn (Base Register): X22 → 10110.
Rt (Source Register): X9 → 01001.
Address Offset: #96 → 96 in binary → 00000110000 (9 bits).

11111000000 00000110000 10110 01001

Hexadecimal: F8003053.

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 Example 2
Final Hexadecimal Codes LDUR X9,[X22,#64]
• LDUR X9, [X22, #64] → F8402853 ADD X9,X21,X9
• ADD X9, X21, X9 → 8B090289 STUR X9,[X22,#96]
• STUR X9, [X22, #96] → F8003053

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 Question from book

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 Example 3
• A[30] = h + A[30] + 1;​
LDUR X9, [X10,#240] // Temporary reg X9 gets A[30]​
ADD X9,X21,X9 // Temporary reg X9 gets h+A[30]​
ADDI X9,X9,#1 // Temporary reg X9 gets h+A[30]+1​
STUR X9, [X10,#240] // Stores h+A[30]+1 back into A[30]

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 Example 4

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 Logical Operators
• Logical operations and shift operations
• R and I format instructions

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 Logical Operations – R format
• The first class of such operations is called shifts.
• They move all the bits in a doubleword to the left or right, filling the emptied
bits with 0s.
• For example, if register X19 contained 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00001001 two = 9ten
• and the instruction to shift left by 4 was executed, the new value would be:
• 00000000 00000000 00000000 00000000 00000000 00000000 00000000
10010000two = 144ten

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 Example – logical shift – R format
• logical shift left (LSL) and logical shift right (LSR)
LSL X11,X19,#4 // reg X11 = reg X19 << 4 bits

• Shifting left by i bits gives the identical result as multiplying by 2 i,

• LSL shifts by 4, which gives the same result as multiplying by 2 4 or 16. The
first bit pattern above represents 9, and 9 × 16 = 144, the value of the second
bit pattern.

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 Example – AND – R format
AND X9, X10, X11 // reg X9 = reg X10 & reg X11
• X11 contains
• 00000000 00000000 00000000 00000000 00000000 00000000 00001101
11000000
• X10 contains
• 00000000 00000000 00000000 00000000 00000000 00000000 00111100
00000000
• The value of register X9 would be
• 00000000 00000000 00000000 00000000 00000000 00000000 00001100
00000000

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 Example – OR, EOR – R format
• Logical OR
• A logical bit-by-bit operation with two operands that calculates a 1 if there is
a 1 in either operand.
• ORR X9,X10,X11 // reg X9 = reg X10 | reg X11
• EOR (Exclusive OR)
• A logical bit-by-bit operation with two operands that calculates the Exclusive
OR of the two operands. It calculates a 1 only if the values are different in the
two operands.
• EOR X9,X10,X12 // reg X9 = reg X10 reg X12

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 LEGv8 CB-format
• Decision making is commonly represented in programming languages using
the if statement, sometimes combined with go to statements and labels.
• LEGv8 assembly language includes two decision-making instructions,
similar to an if statement with a go to.
• The first instruction is:
CBZ register, L1
• This instruction means go to the statement labeled L1 if the value in register
equals zero.
• The mnemonic CBZ stands for compare and branch if zero.

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 LEGv8 CB-format
• The second instruction is:
CBNZ register, L1
• It means go to the statement labeled L1 if the value in register does not equal
zero.
• The mnemonic CBNZ stands for compare and branch if not zero.
• These two instructions are traditionally called conditional branches.

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 LEGv8 B-format
• B Exit
• It means go to the statement labeled EXIT without any condition.

• Unconditional branching – 226 locations for addressing.

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 Example 1 – decisions

SUB X9,X22,X23 // X9 = i − j
CBNZ X9, Else // go to Else if i ≠ j (X9 ≠ 0)
ADD X19,X20,X21 // f = g + h (skipped if i ≠ j)
B Exit // go to Exit
Else:
SUB X19,X20,X21 // f = g − h (skipped if i = j)
Exit:

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 Example 2 – decisions
Loop: LSL X10,X22,#3 // Temp reg X10 = i * 8
X25: while (save[i] == k)
ADD X10,X10,X25 // X10 = address of save[i] i += 1;
LDUR X9, [X10,#0] // Temp reg X9 = save[i]
SUB X11,X9,X24 // X11 = save[i] − k
CBNZ X11, Exit // go to Exit if save[i] ≠ k(X11 ≠ 0)
ADDI X22,X22,#1 // i = i + 1
B Loop // go to Loop
Exit:

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 LEGv8*
• Lessen Extrinsic Garrulity (LEGv8) is a web application that simulates the
assembly, execution, and data path visualization of instructions in the LEGv8
assembly language. It is a subset of the ARMv8 architecture.
• LEGv8 is an interactive educational simulator that helps users understand
computer architecture. It allows users to:
• Analyze changes in registers and memory
• Analyze branching behavior
• Analyze hazard detection and elimination
• Visualize data flow when stepping through instructions
• Select the control and data hazard handling methods to use
• Support both single cycle and pipelined execution

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