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Chapter 10 Bee 3113

The document discusses floorplanning in VLSI circuit design, outlining methods, goals, and objectives for optimizing circuit performance. It covers the distinction between soft and hard blocks, design styles, and various algorithms used in floorplanning. Additionally, it addresses global interconnects and off-chip connections relevant to integrated circuit design.

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14 views27 pages

Chapter 10 Bee 3113

The document discusses floorplanning in VLSI circuit design, outlining methods, goals, and objectives for optimizing circuit performance. It covers the distinction between soft and hard blocks, design styles, and various algorithms used in floorplanning. Additionally, it addresses global interconnects and off-chip connections relevant to integrated circuit design.

Uploaded by

karthi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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BEE 3113 : VLSI CIRCUIT

DESIGN
Chapter 10: Floor-planning.
By : Dr. Noraisyah Tajudin
Email: [email protected]
Faculty of Engineering
Lincoln University College (LUC)
LECTURE 8
DATE : JAN 2024
Contents
• Floor planning Methods
• Global Interconnect
• Floor plan Design
• Off-Chip Connections
RTL Design Flow
Physical Design –Overall Flow
Floorplanning
• Floorplan of an integrated circuit is a
schematic representation of tentative
placement of its major functional
blocks.
• Depending on the design methodology
being followed, the actual definition of
a floorplan may differ.
Why Floorplanning?
The floorplanning problem is to plan the positions and
shapes of the modules at the beginning of the design
cycle to optimize the circuit performance:
• chip area
• total wirelength
• delay of critical path
• routability
• others, e.g., noise, heat dissipation, etc.
Floorplanning
Goals
• Assign shape and location of blocks.
• Decide location of I/O pads.
• Decide location and number of power pads.
• Decide type of power distribution.
• Decide location and type of clock distribution.

Objectives
• Keep highly connected blocks physically close to each other.
• Minimize chip area.
• Minimize delay.
Floorplanning
Input Output
Set of blocks.
Area estimation.
Shapes (Area & Aspect Ratio) and
Possible block shapes.
locations of blocks.
Number of terminals.
Netlist.

Soft Blocks Hard Blocks


• Flexible shape •Fixed shape
• I/O positions not yet determined •Fixed I/O pin positions

8
Design Styles

Full Custom
• Floorplanning is needed.

Standard Cell
• Fixed cell dimensions. Floorplanning translates into a placement problem.
• Floorplanning may be required for large cells if they are partitioned into several
blocks.

Gate Array
• Placement problem.
Slicing and Non-Slicing Floorplan
Slicing Floorplan: Non-Slicing Floorplan:
One that can be One that may not be
obtained by repetitively obtained by repetitively
subdividing (slicing) rectangles
subdividing alone.
horizontally or vertically.
Floorplanning
`
Area

Deadspace

Minimizing area = Minimizing deadspace

Wire length estimation


• Exact wire length not known until after
routing.
• Pin position not known.
• How to estimate?
11
• Center to center estimation.
Floorplanning Algorithm
• Stockmeyer algorithm
• Simulated annealing
• Linear programming
• Sequence-pair based floorplanning
Floorplanning
• Represent floorplan by normalized polish expression.

7 5 4

6
2
1 3

E = 16H7H25HV34HV

13
Encounter Floorplan
Global Interconnects
Off – chip Connections
Structure of a typical package
Solder ball connection
Package structure
Some Packages
Pin inductance
I/O architecture
Input pads
Input pad circuits
Output pad circuits
Three – state pad
Thank You

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