ECT304 -

VLSI CIRCUIT DESIGN

Module 3: Dynamic logic Design
and Storage Cells

 Dynamic Logic Design-

◦ Pre charge- Evaluate logic
◦ Domino Logic,
◦ NP domino logic
 Read Only Memory-4x4 MOS ROM Cell
Arrays(OR,NOR,NAND)
 Random Access Memory –SRAM-Six transistor CMOS SRAM
cell
 DRAM –Three transistor and One transistor Dynamic
Memory Cell.
Design of memory
elements
Semiconductor Memory
Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access
2
E PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM
 2D Memory Architecture
bit line
2K-L
(BL)
word line
Row Address

AL (WL)
AL+1
Decoder
storage
AK-1 (RAM) cell
Row
significant bits)

M2L
A0
Address
Column

selects appropriate
(least

A1 Column Decoder
AL-1 word from memory
Sense Amplifiers row
amplifies bit line
swing
Read/Write Circuits

Input/Output (M
bits)
ROM
 Read only memories are used to store constants, control information
and program instructions in digital systems.
 They may also be thought of as components that provide a fixed,
specified binary output for every binary input.
 Thus storing binary information at a particular address location can
be achieved by the presence or absence of a data path from the
selected row (word line) to the selected column (bit line), which is
equivalent to the presence or absence of a device at that particular
location.
 The two different types of implementations of ROM array are:
◦ NOR-based ROM array
◦ NAND-based ROM array
 4x4 NOR based ROM array
VDD
Pull-up devices

WL[0]

GND
WL[1]

WL[2]

GND
WL[3]

BL[0] BL [1] BL [2] BL [3]

 4x4 NOR based ROM array
VDD
Pull-up devices

WL[0]

GND
WL[1]

WL[2]

GND
WL[3]

BL[0] BL [1] BL [2] BL [3]

NOR based ROM array
 Each memory cell is represented by one nMOS transistor
 A binary information is stored by connecting or not the drain terminal of such a
transistor to the bit line.
 For every row address only one word line is activated by applying a high signal to
the gates of nMOS transistors in a row.
 If a selected transistor in the i-th column is connected to a bit line then the logic ‘0’
is stored in this memory cell.
 If the transistor is not connected, then the logic ‘1’ is stored.
 Here, each column consists of a pseudo nMOS NOR gate driven by some of the
row signals, i.e., the word line.
 Only one word line is activated at a time by raising its voltage to VDD, while all
other rows are held at a low votlage level.
 If an active transistor exists at the cross point of a column and the selected row,
the column voltage is pulled down to the logic LOW level by that transistor.
 If no active transistor exists at the cross point, the column voltage is pulled HIGH
by the pMOS load device.
 logic "1"-bit is stored -absence of an active transistor
 logic "0"-bit is stored -presence of an active transistor
OR based ROM array
BL[0] BL[1] BL[2] BL[3]

WL[0]
VDD
WL[1]

WL[2]
VDD

WL[3]

Vbias

Pull-down loads
 NAND based ROM array
VDD
Pull-up devices

BL[0] BL[1] BL[2] BL[3]

WL[0]

WL[1]

WL[2]

WL[3]

All word lines high by default with exception of selected row

 NAND based ROM array
VDD
Pull-up devices

BL[0] BL[1] BL[2] BL[3]

WL[0]

WL[1]

WL[2]

WL[3]

All word lines high by default with exception of selected row

 NAND based ROM array
 For every row address only one word line is activated by applying a low
signal to the gates of nMOS transistors in a row.
 When no word line is activated, all nMOS transistors are on and the line
signals are all low.
 When a word line is activated all transistors in the row are switched off and
the respective signals are high.
 If a transistor in the selected row is short-circuited, then the respective Ci
signal is low.
 In other words, the logic ‘0’ is stored when a transistor is replaced with a
wire, whereas the logic ‘1’ is stored by an nMOS transistor being present.
NAND based ROM array
 We have up to n serially connected nMOS transistors in each
column.
 Each bit line consists of a depletion-load NAND gate, driven by
some of the row signals, i.e. the word lines.
 In normal operation, all word lines are held at the logic HIGH voltage
level except for the selected line, which is pulled down to logic LOW
level.
 If a transistor exists at the cross point of a column and the selected
row, that transistor is turned off and column voltage is pulled HIGH
by the load device. On the other hand, if no transistor exists
(shorted) at that particular cross point, the column voltage is pulled
LOW by the other nMOS transistors in the multi-input NAND
structure.
 Thus, a logic "1"-bit is stored by the presence of a transistor that can
be deactivated, while a logic "0"-bit is stored by a shorted or
normally ON transistor at the cross point.
 Read-Write Memories (RAM
 STATIC (SRAM)

Data stored as long as supply is applied

Large (6 transistors/cell)
Fast
Differential

 DYNAMIC (DRAM)

Periodic refresh required

Small (1-3 transistors/cell)
Slower
Single Ended
6-Transistor CMOS SRAM
cell
 The 6T SRAM cell contains a pair of cross-coupled
inverters (M1,M2 and M3,M4) holding the state and a
pair of access transistors (M5,M6) to read or write the
state.
 The positive feedback corrects disturbances caused by
leakage or noise.
 The cell is written by driving the desired value and its
complement onto the bitlines, BL and BL_b, then raising
the wordline, word. The new data overpowers the cross-
coupled inverters.
 It is read by precharging the two bitlines high, then
allowing them to float. When word is raised, BL or BL_b
pulls down, indicating the data value.
 The central challenges in SRAM design are minimizing its
size and ensuring that the circuitry holding the state is
weak enough to be overpowered during a write, yet
strong enough not to be disturbed during a read.
6-transistor CMOS SRAM Cell

WL

VDD
M2 M4
Q
M5 Q M6

M1 M3

BL BL
CMOS SRAM Analysis (Read)
WL

VDD
BL M4
BL
Q= 0
Q= 1 M6
M5

VDD M1 VDD V DD

Cbit Cbit
CMOS SRAM Analysis
(Read)
1.2
1
Voltage Rise (V)

0.8
0.6
0.4
0.2[V]
Voltage rise
0
0 0.5 11.2 1.5 2 2.5 3
Cell Ratio (CR)
CMOS SRAM Analysis
(Write) WL
VDD
M4

Q= 0 M6
M5 Q= 1

M1
VDD
BL = 1 BL = 0
CMOS SRAM Analysis
(Write)
3-Transistor DRAM Cell
BL 1 BL 2

WWL

RWL WWL

M3 RWL

M1 X X V DD 2 V T
M2
V DD
CS BL1

BL2 V DD 2 V T DV

No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = WWL
V -VTn
1-Transistor DRAM Cell
BL
WL Write 1 Read 1
WL

M1
X GND V DD 2 V T
CS
V DD
BL
V DD /2 V
sensing
CBL

Write: CSis charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
DV = VBL – V PRE = V BIT – V PRE ------------
C S + CBL

Voltage swing is small; typically around 250 mV.

Sense Amp Operation

V BL V (1)

V
PRE
DV(1)

V(0)
Sense amp activated t
Word line activated
 1-T DRAM Cell
Capacitor

M 1 word
line
Metal word line
SiO2
Poly
n+ n+ Field Oxide Diffused
bit line
Inversion layer
Poly
induced by Polysilicon
Polysilicon
plate bias gate plate

Cross-section Layout

Uses Polysilicon-Diffusion Capacitance

Expensive in Area
Reference
1. Jan M. Rabaey, A. Chandrakasan, B.
Nikolic, Digital Integrated Circuits- A
Design perspective, 2/e, Pearson
education
2. Weste and Eshraghian, Principles of
CMOS VLSI Design, A Systems
Perspective,2/e, Pearson Education
3. Neil H. E. Weste, David Money Harris,
CMOS VLSI Design- Circuits and
Systems Perspective, 4/e, Pearson
education