Interfacing I/O Devices

Basic Interfacing Concepts

 The I/O devices (Keyboards, displays etc.) are the ears and eyes of the MPUs.
 The I/O devices are the communication channels to the outside world.
There are two I/O modes in data communication:
Parallel I/O mode: In this mode, data can enter or exit in groups of eight bits using
the entire data bus.
Serial I/O Mode: In this mode, one bit is transferred using one data line, i.e. Data is
transferred as a one bit at a time using one data line.
In the parallel I/O mode, the devices can be interfaced using two techniques:
Peripheral-mapped I/O: In this technique, a device is identified with an 8-bit address
and enabled by I/O-related control signals. The instruction
IN/OUT are used for data transfer.
Memory-mapped I/O: In this technique, a device is identified with a16-bit address
and enabled by memory-related control signals. The instruction
LDA/STA are used for data transfer.
The process of data transfer in both techniques is identical.
Each device is assigned a binary address, called a device address or port number,
through its interfacing circuit.
 Peripheral I/O Instructions

Opcode Operand Description

OUT 8-bit port Address This is a two-byte instruction with the

OUT 01H (Mnemonics) hexadecimal opcode D3, and the
second byte is the port address of an
output device.
This instruction transfers (copies) data from the accumulator to the output device.

To display the contents of the accumulator at an output device (such as LEDs) with
the address, for example, 01H, the instruction will be written and stored in memory
as follows:

Memory Machine Memory

Address Code Mnemonics Contents

2050 D3 OUT 01H ; 2050 1 1 0 1 0 0 1 1 = D3H

2051 01
; 2051 0 0 0 0 0 0 0 1 = 01H
 Timing for Execution of OUT Instruction

M1 (Opcode Fetch) M2 (Memory Read) M3 (I/O Write)

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

A15-A8 20H Unspecified 20H Port Address 01H

Port Accumulator
AD7-AD0 50H Opcode D3H 51H 01H Address 01H Contents

ALE

IO/M

RD

MEMR

WR

IOW
 Peripheral I/O Instructions

Opcode Operand Description

IN 8-bit port Address This is a two-byte instruction with the

IN 84H (Mnemonics) hexadecimal opcode DB, and the
second byte is the port address of an
input device.
This instruction reads (copies) data from an input device and places/store the data
byte in the accumulator.
To read switch positions, for example, from an input port with the port address 84H,
the instruction will be written and stored in memory as follows:

Memory Machine Memory

Address Code Mnemonics Contents

2065 DB IN 84H ; 2065 1 1 0 1 1 0 1 1 = DBH

2066 84
; 2066 1 0 0 0 0 1 0 0 = 84H
 Timing for Execution of IN Instruction

M1 (Opcode Fetch) M2 (Memory Read) M3 (I/O Read)

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

A15-A8 20H Unspecified 20H Port Address 84H

Port Data from

AD7-AD0 65H Opcode DBH 66H 84H Address 84H Input Port

ALE

IO/M

RD

MEMR

IOR
 Device Selection and Data Transfer

• Decode the address bus to generate a unique pulse corresponding to the

device address on the bus; this is called the device address pulse or I/O pulse.

• Combine (AND) the device address pulse with the control signal to generate a
device select (I/O select) pulse that is generated only when both signals are
asserted.

• Use the I/O select pulse to activate the interfacing device (I/O port).

The following block diagram illustrates these steps for interfacing an I/O device:
 Device Selection and Data Transfer

Data Latch To Peripheral

Bus Or
Buffer
Address Device or I/O
Lines Decoder Address Pulse
(A7-A0)
IOADR Enable
IOSEL
Control AND
Signal Device Select Pulse
(IOR or IOW)

Figure-3: Block Diagram of I/O Interface

 Practical Decode Logic for LED Output Port

A7 +Vcc

A6
A5 I/O Address Pulse D7 D7
Data Latch
A4 G1 Bus
A3 D0 D0
IOADR
A2

A1 Latch Enable

A0
IOSEL
G2
IOW Device Select Pulse
Control Signal

Figure-4: Decode logic for LED port

In this figure, all eight lines are decoded to generate one unique pulse; the device
will be selected only with the address, 01H. This is called absolute decoding and
is a good design practice.
 Linear-Select Decoding

To minimize the cost, the output port can be selected by using one address line,
as shown in following figure; this is called linear-select decoding. As a result, the
device has multiple addresses. In this figure, address line A0 and control signal
IOW are combined to generate the device select pulse. This port will be addressed
whenever A0 = 0. Lines A1 through A7 are unused and can assume don’t care
states.
+Vcc

D7 D7
Data Latch
Bus
D0 D0

Latch Enable

A0 IOSEL
G2
IOW Device Select Pulse Figure-5: Linear-Select Decoding: Device
Control Signal with Multiple Address.
 Input Interfacing
+Vc

A7
DIP
A6 Switches
D7
A5
Tri-State Data Bus
A4 G1 Buffer
A3
IOADR D0
A2

A1 Enable

A0
IOSEL
G2
IOR Device Select Pulse
Control Signal

Figure-6: Decode Logic for a Dip-Switch Input Port.

 Interfacing I/Os Using Decoders

+ 5V

A6
A5
A7
A4
A3 + 5V
Data Tri-State
Bus Buffer
IOR
E1 E2 E3 EN
MSB
A2 3-to-8 IOSEL
A1 Decoder FAH
Q2
A0
F8H
Q0
Data + 5V
Bus Latch

EN
IOSEL
IOW

Figure-7: Addressing Decoding Using 3-to-8 Decoder.

 Interfacing Output Displays

Example – 1: Simple display of binary data with LEDs.

Problem Statement

1. Design a interfacing LED output port with the device address FFH, using
7475 D-type latch or 74LS373 octal D-type latch, a 74LS30 8-input NAND
gate, a 74LS02 NOR gate and LEDs.
2. Explain the similarities between the circuits using 7475 D-type latch and
74LS373 octal D-type latch.
3. Write instructions to display binary data at the port.

Circuit Analysis

• Address bus A7 – A0 is decoded by using 8-input NAND gate.

• The output of the NAND gate goes low only when the address lines carry
the address FFH.
• The output of the NAND gate is combined with the microprocessor control
signal IOW in a NOR gate (connected as negative AND gate)
 Interfacing Output Displays

Circuit Analysis
• The output of the NOR gate goes high to generate an I/O select pulse when
both inputs are law (or both signals are asserted)
• Meanwhile, the contents of the accumulator have been put on the data bus.
• The I/O select pulse is used as a clock pulse to activate the D-type latch,
and the data are latched and displayed.
Similarities between the interfacing circuits

• The interfacing circuits using 7475 D-type latch and 74LS373 octal D-type
latch are functionally similar.
• The 74LS373 includes D-latches followed by tri-state buffers.
• This device has two control signals: Enable (G) to clock data in the flip-flops
and Output Control (OC) to enable the buffers.

N.B. : In this circuit, the output Q of the latch is used instead of the output Q.
Resistors are used to limit the current flow through the LEDs.
 Interfacing Output Displays

Program
Address Machine
(LO) (Code) Mnemonics Comments
00 3E MVI A, DATA ; Load accumulator with data
01 DATA*
02 D3 OUT FFH ; Output accumulator contents to
; port FFH
03 FF
04 HLT ; End of program

Program Description
• Instruction MVI A, DATA loads the accumulator with the DATA you enter.
• Instruction OUT FFH identifies the LED port as the output device and displays
the data.
• Instruction HLT ends the program.

* Enter data you wish to display

 Interfacing Output Displays

A7
A6
74LS30
A5
+ 5V
A4
A3 Data Bus + 5V

A2 D7
A1 D6
7475
A0 D5 D-Latch

D4
IOSEL
1/4 74LS02

D3
D2
7475
IOW
D1 D-Latch

D0
Figure-8: (a) Interfacing LED
Output Port Using the 7475
D-Type Latch.
+ 5V
 Interfacing Output Displays

+ 5V

+ 5V

D7 D Q
CLK
D6

D5

D4
74LS373
D3 Octal
Latch
D2

D1

D0
G OC

From
74LS02
I/O Select Pulse Figure-8: (b) Interfacing LED Output Port Using the
with address FF 74LS373 Octal D-Type Latch.
 Interfacing Output Displays

Example – 2: Seven-Segment LED Display

Problem Statement

1. Design a seven-segment LED output port with the device address F5H,
using a 74LS138 3-to-8 decoder, a 74LS373 octal latch, a 74LS20 4-input
NAND gate, a 74LS02 NOR gate, and a common-anode seven-segment
LED.
2. Given WR and IO/M signals from the 8085, generate the IOW control signal.
3. Explain the binary codes required to display 0 to F Hex digits at the seven-
segment LED.
4. Write instructions to display digit 7 at the port.

Seven-Segment
• A seven-segment LED consists of seven light-emitting diode segments and
one segment for the decimal point. The LEDs are arranged as shown in fig.
• To display a number, the necessary segments are lit by sending an
appropriate signal for current flow through diodes.
 Interfacing Output Displays

Seven-Segment
• A seven-segment LED consists of seven light-emitting diode segments and
one segment for the decimal point. The LEDs are arranged as shown in
figure-9 (a).
• To display a number, the necessary segments are lit by sending an
appropriate signal for current flow through diodes. For example, to display
an 8, all segments must be lit.
• Seven-segment LEDs are available in two types: common cathode and
common anode. They can be represented schematically as in figure-9 (b)
and (c). Current flow in these diodes should be limited to 20 mA.
• The seven segments, A through G, are usually connected to data lines D0
through D6, respectively. If the decimal-point segment is being used, data
line D7 is connected to DP; otherwise it is left open.

The binary code required to display a digit is determined by the type of the
seven-segment LED (common cathode or common anode), the connection
of the data lines, and the logic required to light the segment.
 Interfacing Output Displays

F B
G

E C
Common Anode D DP To Data lines through an interface Device
D7 D6 D5 D4 D3 D2 D1 D0
(a)

DP G F E D C B A

DP G F E D C B A

D7 D6 D5 D4 D3 D2 D1 D0
To Data lines through an interface Device Common Cathode
(b) (c)
Figure-9 Seven-Segment LED: (a) LED Segments; (b) Common-Anode LED; (c) Common-Cathode LED
 Interfacing Output Displays

To display digit 7 at the LED in figure-10, the requirements are as follows:

1. It is a common-anode seven-segment LED, and logic 0 is required to turn on
a segment.
2. To display digit 7, segments A, B, and C should be turn on.
3. The binary code should be

Data Lines D7 D6 D5 D4 D3 D2 D1 D0
Bits X 1 1 1 1 0 0 0 = 78H
Segments NC G F E D C B A

The code for each digit can be determined by examining the connections of the
data lines to the segments and the logic requirements.
 Interfacing Output Displays

Interfacing Circuit and Its Analysis

To design an output port with the address F5H, the address lines A7 – A0 should
have the following logic:
A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 0 1 0 1 = F5H
This can be accomplished by using A2, A1, and A0 as input lines to the decoder,
A3 can be connected to active low enable E1, and the remaining address lines
can be connected to E2 through the 4-input NAND gate. Figure-10 shows an
output port with the address F5H.
• The output Q5 of the decoder is logically ANDed with the control signal IOW
using the NOR gate (74LS02).
• The control signal IOW is generated by logically ANDing IO/M and WR
signals in the negative NAND gate (physically or gate 74LS32).
• The output of the NOR gate is the I/O select pulse that is used to enable the
latch (74LS373).
 Interfacing Output Displays

Program/Instructions
The following instructions (program) are necessary to display digit 7 at the
output port F5H:

MVI A, 78H ; Load the seven-segment code in the accumulator

OUT F5H ; Display digit 7 at port F5H
HLT ; End

• The first instruction loads the binary code of 78H in the accumulator which is
necessary to display digit 7 at the common-anode seven-segment LED
• The second instruction sends the contents of the accumulator (78H) to the
output port F5H.

When the 8085 microprocessor executes the OUT instruction, the digit 7 is
displayed at the port as follows:
 Interfacing Output Displays

+ 5V

D7 74LS373
D6 Latch
D5
A7 D4 3/8
A6 D3 + 5V
A5 + 5V 15
A4 D2
16
D1
A3 19
D0 LE OE
E1 E2 E3
A2
Q5 Current Common Anode
A1
Limiting Seven-Segment LED
A0 3-to-8 IOSEL Resistors
Decoder 74LS02

IO/M IOW
WR
74LS32
Figure-10: Interfacing Seven-Segment LED
 Interfacing Input Devices

Example: Data Input from DIP Switches

 Interfacing Input Devices

+ 5V

74LS244 1 S7
A7 D7
A6 Octal 1 S6
A5 Buffer 1 S5
Data 1 S4
E1 E2 E3 Bus 1 S3
MSB
A2 0 S2
3-to-8 Q4 IOADR
A1 0 S1
Decoder
0 S0
D0
74LS138 OE

IOSEL

IO/M
RD IOR Figure-11 Interfacing DIP Switches
 Memory-Mapped I/O

 In Memory-mapped I/O, the input and output devices are assigned and
identified by 16-bit address.

 In this technique, memory-related instructions (such as LDA, STA, etc.) and

memory control signals ( MEMR and MEMW )are used to transfer data between
the MPU and I/O devices.

 The microprocessor communicates with an I/O device as if it was one of the

memory locations.
The following instruction is an example to transfer the contents of the accumulator
to the memory location 8000H.

Memory Hex Mnemonics Comments

Address Code
2050 32
2051 00 STA 8000H; Store contents of accumulator in memory
location 8000H.
2052 80
 Memory-Mapped I/O

Similarly, the following instruction is an example to load the accumulator with the
contents of location 4000H.
Memory Hex Mnemonics Comments
Address Code
2060 3A
2061 00 LDA 4000H; Load the accumulator with the contents
of location 4000H.
2062 40
In the first example, if an output device, instead of a memory register, is connected
at this address, the accumulator contents will be transferred to the output device.
This is called the memory-mapped I/O technique. Same thing will be happened in
the 2nd example, but in this case, the data will transferred from the input device to
the accumulator.
Device selection and data transfer in memory-mapped I/O require three steps that
are similar to those required in peripheral-mapped I/O.
• Decode the address bus to generate the device address pulse
• And the control signals with the device address pulse to generate the device
select (I/O select) pulse.
• Use the device select pulse to enable the I/O port.
 Timing for Execution of the Instruction
STA 8000H
M1 (Opcode Fetch) M2 (Memory Read) M3 (Memory Read) M4 (Memory Write)
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3

A15-A8 20H 20H 20H 80H

Unspecified
Opcode

AD7-AD0 50H 32H 51H 00H 52H 80H 00H Data

Accumulator
Contents

ALE

IO/M

RD

WR

MEMW
 Timing for Execution of the Instruction
LDA 4000H
M1 (Opcode Fetch) M2 (Memory Read) M3 (Memory Read) M4 (Memory Read)
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3

A15-A8 20H 20H 20H 40H

Unspecified
Opcode
Data from
AD7-AD0 60H 32H 61H 00H 62H 40H 00H Input port

ALE

IO/M

RD

MEMR
Memory-Mapped I/O Interfacing
 Memory-Mapped I/O Interfacing

+ 5V
A15
A14
A13
D7
A12
A11
A10 Data
A9 B7H
A3 Bus
A8
A7
D0 OE
A6
A5 E1 E2 E3
A4 A2 FFF9H
A1 + 5V
A0 Q1
MEMR
Q0 FFF8H
Solid State
MEMW
D7 LE OE Relay Cooling System
Heating System
Fire Alarm
Data PA System
48H Lights
Bus
Fire Exit Gate
Entry Gate
D0 Relay Exit Gate
Programmable Interface Devices
 Basic Concepts in Programmable Devices

Execution speed of the microprocessor is much faster than the response of

the peripheral.

Requirements for a programmable interfacing devices as follows:

The device should include

1. input and output registers ( a group of latches to hold data).
2. tri-state buffers.
3. Capability for bidirectional data follow.
4. handshake and interrupt signals.
5. control logic.
6. chip select logic
7. interrupt control logic.
 Making the 74LS245 Transceiver Programmable

Making 74LS245 programmable

74LS245 Bidirectional
Buffer
 Programmable Device with a Status Register

A Hypothetical Programmable Device with a Status Register

 Programmable Devices with Handshake Signals

The MPU and peripherals operate at different speeds; therefore, signals

are exchanged prior to data transfer between the fast-responding MPU
and slow responding peripherals such as printers and data converters.
These signals are called handshake signals.
 Data Input with Handshake

The steps in data input from a peripheral such as a keyboard are as follows:

1. A peripheral strobes or places a data byte in the input port and informs the
interfacing device by sending handshake signals STB (Strobe).

2. The device informs the peripheral that its input is full do not send the next
byte until this one has been read. This message is conveyed to the peripheral
by sending handshake signal IBF (Input Buffer Full).

3. The MPU keeps checking the status until a byte is available. Or the interfacing
device informs the MPU, by sending an interrupt, that it has a byte to be read.

4. The MPU reads the byte by sending control signal RD.

 Data Output with Handshake

The steps in data output to a peripheral such as a printer are as follows:

1. The MPU writes a byte into the output port of the programmable device by
sending control signal WR.

2. The device informs the peripheral by sending handshake signal OBF (Output
Buffer Full), that a byte is on the way.

3. The peripheral acknowledges the byte by sending back the ACK (Acknowledge)
signal to the device.

4. The device interrupts the MPU to ask for the next byte, or the MPU finds out that
the byte has been acknowledged through the status check.
+Vcc