Microprocessor Architecture

Microprocessing Unit (MPU)

 The term microprocessing unit (MPU) is similar to the term

central processing unit (CPU) used in traditional computers.

 MPU is defined as a device or a group of devices (as a unit)

that can communicate with peripherals, provide timing
signals, direct data flow, and perform computing task as
specified by the instructions in memory.

 The unit will have the necessary lines for the address bus,
the data bus, control and status signals, and would require
only a power supply and a crystal (or equivalent frequency-
determining component) to be completely functional.
 Microprocessing Unit (MPU)

Using the above description, the 8085 microprocessor can almost

qualify as an MPU, but the following two limitations. These are:

1. The low-order address bus of the 8085 microprocessor is

multiplexed (time-shared) with the data bus. The buses need
to be demultiplexed.

2. Appropriate control signals need to be generated to interface

memory and I/O with the 8085 microprocessor.

Intel has some specialized memory and I/O devices that do not
require such control signals.
 Pinout and Signals

 All the signals can be classified into six

groups:

1. Address Bus
2. Data Bus
3. Control and Status Signals
4. Power Supply & Frequency Signals
5. Externally Initiated Signals, and
6. Serial I/O Ports.

The 8085 Microprocessor Pinout and Signals

 Pinout and Signals
Power & Frequency Signals GND
+5 V

1 2 40 20
SID 5 X1 X 2 VCC VSS
Serial
I/O SOD 4 A15 28
Ports High-Order
TRAP 6 21 Address Bus
A8
RST 7.5 7
RST 6.5 8
RST 5.5 9 19
Multiplexed
INTR 10
Externally
8085A AD7 Address/Data
Initiated
8 Bus
12
Signals READY 35
30
HOLD 39 ALE
തതതതതതതതതതതത
AD0
RESET IN36
29
S0
33
S1
തതതതതതത
INTA ഥ
IO/M
34 Control and Status Signal
External Signal 11
തതതത
RD
Acknowledgement HLDA 32
38
തതതതത
WR
31

3 37
RESET CLK
OUT OUT
 Pinout and Signals

ADDRESS BUS
The 8085 has eight signal lines, A15 – A8, which are unidirectional and used
as the high order address bus.
MULTIPLEXED ADDRESS/DATA BUS
The signal lines AD7 – AD0 are bidirectional and serve a dual purpose, that
is, they are used as the low-order address bus as well as the data bus. In
executing an instruction, during the earlier part of the cycle, these lines
are used as the low-order address bus. During the later part of the cycle,
these lines are used as the data bus. This is also known as multiplexing
the bus.

CONTROL AND STATUS SIGNALS

This group of signals include two control signals (RD and WR), three
status signals (IO/M, S1 and S0) to indicate the nature of operations, and
one special signal (ALE) to indicate the beginning of the operation. These
signals are as follows:
 Pinout and Signals

CONTROL AND STATUS SIGNALS

 ALE – Address Latch Enable: This is a positive going pulse generated
every time the 8085 begins an operation (machine cycle); it indicates
that the bits on AD7 – AD0 are address bits. This signal is used
primarily to latch the low-order address from the multiplexed bus and
generate a separate set of eight address lines, A7 – A0.
 RD – Read: This is a Read control signal (active low). This signal
indicates that the selected I/O or memory devices is to be read and
data are available on the data bus.
 WR – Write: This is a Write control signal (active low). This signal
indicates that the data on the data bus are to be written into a selected
memory or I/O location.
 IO/M: This is a status signal used to differentiate between I/O and
memory operations. When it is high, it indicates an I/O operation;
when it is low, it indicates a memory operation. This signal is
combined with RD (Read) and WR (Write) to generate I/O and memory
control signals.
 Pinout and Signals

 S1 and S0: These status signals, similar to IO/M, can identify various
operations, but they are rarely used in small systems. All the
operations and their associated status signals are listed in the
following table.

8085 Machine Cycle Status and Control Signals

Status
Machine Cycle IO/M S1 So Control Signals

Opcode Fetch 0 0 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
I/O Read 1 1 0 RD = 0
I/O Write 1 0 1 WR = 0
Interrupt Acknowledge 1 1 1 INTA = 0
Halt Z 0 0
Hold Z X X RD, WR = Z and
Note:
ResetZ = Tri-state (High Impedance) Z X X INTA = 1
X = Unspecified
 Pinout and Signals

POWER SUPPLY AND CLOCK FREQUENCY

The power supply and frequency signals are as follows:

 VCC: +5V power supply.

 VSS: Ground Reference.
 X1, X2: A crystal (or RC, LC network) is connected at these two
points. The frequency is internally divided by two; therefore, to
operate a system at 3 MHz, the crystal should have a frequency
of 6 MHz.
 CLK (OUT) – Clock Output: This signal can be used as the
system clock for other devices.
EXTERNALLY INITIATED SIGNALS INCLUDING INTERRUPTS
The 8085 has five interrupt signals that can be used to interrupt a program
execution. To respond to the interrupt requests, the microprocessor has
interrupt acknowledge signal, INTA. In addition to the interrupts, three
pins – RESET, READY and HOLD – accept the externally initiated signals
as inputs. To respond to the HOLD request, it has one signal called HLDA
( Hold Acknowledge). These signals are as follows:
EXTERNALLY INITIATED SIGNALS INCLUDING INTERRUPTS

 INTR (Input) - Interrupt Request: This is used as a general-purpose

interrupt.
 INTA (Output) - Interrupt Acknowledge: This is used to acknowledge
an interrupt
 RST 7.5, RST 6.5 & RST 5.5 (Inputs) – Restart Interrupts: These are
vectored interrupts and transfer the program control to the specific
memory locations. They have higher priorities than the INTR
interrupt. Among these three, the priority order is 7.5, 6.5, and 5.5.
 TRAP (Input): This is a nonmaskable interrupt and has the highest
priority.
 HOLD (Input): This signal indicates that a peripheral such as a DMA
(Direct memory Access) controller is requesting the use of the data
address buses.
 HLDA (Output) – Hold Acknowledge: This signal acknowledges the
HOLD request.
EXTERNALLY INITIATED SIGNALS INCLUDING INTERRUPTS
 READY (Input): This signal is used to delay the microprocessor
Read or Write cycles until a slow-responding peripheral is ready to
send or accept data. When this signal goes low, the microprocessor
waits for an integral number of clock cycles until it goes high.
 RESET IN: When the signal on this pin goes low, the program
counter is set to zero, the buses are tri-stated, and the MPU is reset.
 RESET OUT: This signal indicates that the MPU is being reset. The
signal can be used to reset other devices.

SERIAL I/O PORTS

 B C
Instruction
ALU D E
Decoder
H L
Stack pointer
Control Program counter
logic

4F

Figure: Data Flow from Memory to the MPU

 Opcode Fetch

T1 T2 T3 T4

CLK

A15 High-Order
20H Unspecified
Memory Address
A8

AD7
05H 4FH Opcode
AD0 Low-Order
Memory Address

ALE

ഥ
𝐈𝐎/𝐌

Status ഥ = 0, S0 = 1, S1 = 1
𝐈𝐎/𝐌 Opcode Fetch

തതതത
𝐑𝐃
 A15

A8
ALE

AD7 D Q

8085
Microprocessor

AD0
 IO/M

8085 RD

WR