“Advance Digital

Electronics”
Presented by VLSI Batch -2025

1
 Topics
 SOP and POS  Setup Time and Hold Time
 Combinational and Sequential  Glitches and Hazards
Circuit  Shift Registers
 ASCII Encoder  FIFO
 Decimal to Binary Encoder  Memories
 4-Bit Carry Look-Ahead Adder  CMOS
(CLA)
 NAND gate And NOR Gate using
 Flipflop Converter CMOS
 Counters

2
“SOP and POS”

3
 Definition of SOP and POS
SOP (Sum of Products) and POS (Product of Sums) are core
concepts in Boolean Algebra.
 SOP : Sum (OR) of product terms (AND).
 POS :Product (AND) of sum terms (OR).
Both simplify Boolean expressions and are used in Karnaugh
Maps (K-maps).
What is SOP?  What is POS?
SOP stands for Sum of Products.  POS stands for Product of Sums (Not included
It is the sum (OR operation) of minterms above, but complementary for explanation).
in Boolean expressions.  Represents the product (AND operation) of
Denoted by the symbol ∑ in equations. maxterms, using sum terms.
Works on active high logic, meaning it  Works on active low logic, meaning it focuses on
represents conditions where variables are conditions where variables are false (0).
true (1).  Example format: (A + B)·(B + C)·(C + D).
Example format: A·B + B·C + C·D.

 Applications
 Used for minimizing Boolean
expressions.
 Widely applied in K-map
4
simplifications for designing
SOP in K-Map
• The below image represents the SOP in K-map. Example:
•F=1 for minterms m1 and m3​.
CD C’D’ C’D CD CD’ Step 1: Identify Minterms
AB 00 01 11 10 •m1=A′B′C′D
•m3=A′B′CD
A’B’ A’B’C’D’ A’B’C’D A’B’CD A’B’CD’
00
Step 2: K-map Representation
0 1 3 2
CD=00 CD=01 CD=11 CD=10
A’B AB=00 0 1 1 0
A’BC’D’ A’BC’D A’BCD A’BCD’
01 4 5 7 6 AB=01 0 0 0 0

AB AB=11 0 0 0 0
11 ABC’D’ ABC’D ABCD ABCD’ AB=10 0 0 0 0
12 13 15 14
AB’ Step 3: Simplify
10 AB’C’D’ AB’C’D AB’CD AB’CD’ Final SOP Expression:
8 9 11 10
F=A′B′D
SOP(MINTERMS)
5
 POS in K-Map
Example:
• The below image represents the POS in K-map. F=0for maxterms M0​and M2.
Step 1: Identify Maxterms
C+D’ C’+D’ •M0=A+B+C+D
CD C+D C’+D
01 11 •M2=A+B+C′+D
AB 00 10
Step 2: K-map Representation

A+B+C+D A+B+C+D’ A+B+C’+D’ A+B+C’+D C+D C+D C+D C+D=

A+B 00 =00 =01 =11 10
0 1 3 2
A+B=00 0 1 0 1
A+B’ 01 A+B’+C+D A+B’+C+D A+B’+C’+D’ A+B’+C’+D A+B=01 1 1 1 1
4 5 7 6 A+B=11 1 1 1 1
A+B=10 1 1 1 1
A+B’ 11 A’+B’+C+D’ A’+B’+C+D’ A’+B’+C’+D’ A’+B’+C’+D
8 9 11 10
Final POS Expression:
F=(A+B+C+D)(A+B+C′+D’)
A’+B 10 A’+B+C+D A’+B+C+D’ A’+B+C’+D’ A’+B+C’+D
12 13 15 14
POS(MAXTERMS)
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 SOP vs POS

Characterization SOP POS

Definition SOP is sum of minterms. POS is product of maxterms.

Stands for Sum of product Product of sum

It works on low logic
Logic It works on high logic

Denotation By Σ. By П.

Output Sum of all product is 1. product of all sum is 0.

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“Combinational and Sequential Circuit”

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What is Combinational Circuit?
• A Combinational circuit is a type of digital circuit where the output
depends only on the current inputs. It doesn't have memory or
store any past information.

Examples
Combinational
• Adders, Subtractors I Logic I
n input I I m output
• Multipliers, Dividers variables I Circuit I variables

• Multiplexers, Demultiplexers
• Encoders, Decoders
• Comparators, Parity generators
• All types of Code Converters etc.

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 What is Sequential Circuit?
• A Sequential circuit is a type of digital circuit where the output depends on
both the current inputs and past inputs. It has storage elements like flip-
flops or latches to remember previous states.

Examples
• Flip-Flops Sequential
n input I Logic I
m output
• Registers variables
I
I Circuit
I
I variables
I I
• Counters
• Shift Registers
Clock Pulses
• Finite State Machines (FSMs)
• Timers
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 Combinational Circuits VS. Sequential Circuits

Combinational Circuits Sequential Circuits

1.) A type of digital circuit where the output is 1.) A type of digital circuit where the output
only a pure function of the present input. depends on both present and the sequence of
past inputs.

2.) Output depends on the present input. 2.) Output depends on the present input and
past output.

3.) There is no memory unit. 3.) There is a memory unit to store immediate
results.

4.) There is no clock. 4.) There is a clock.

Examples: Half Adder, Full Adder, Multiplexer, Examples: Flip flops and Registers.
Demultiplexer etc.

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 ASCII Encoder
(American Standard Code for Information Interchange)

12
 ASCII Encoder
• Converts Alphanumeric characters, symbols, and control signals into
their corresponding ASCII numerical values. These numerical values
are then represented in binary form.

• Example
Input : A
ASCII Value : 65
Binary Output : 1 0 0 0 0 0 1

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• Total no of Combinations are 128 ( 0 to 127) than we need a total 7 Pins ( 0 to 6) in Output.

I0
I1
I2
I3
I4
I5 O0
.
. O1
.
.
O2
INPUT .
.
O3 OUTPUT
.. O4
.
. O5
.
. O6
I122
I123
I124
I125
I126
I127

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 ASCII Table

Starting Three Bits Last Four Bits

0 1 2 3 4 5 6 7 8 9 A B C D E F
0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT EF CR SO SI
1 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US
2 ! " # $ % & ' ( ) * + , - . /
3 0 1 2 3 4 5 6 7 8 9 : ; < > ?
4 @ A B C D E F G H I J K L M N O
5 P Q R S T U V W X Y Z [ \ ] ^ _
6 ` a b c d e f g h i j k l m n o
7 p q r s t u v w x y z { | } ~ DEL

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“Decimal to Binary Encoder”
Using 8:3 encoder

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• Truth Table

INPUT OUTPUT
D B3 B2 B1 B0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
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CIRCUIT DIAGRAM
D1 D2 D3 D4 D5 D6 D7 D8 D9
B3

B2

B1

B0

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Steps for achieve the Binary o/p equation

1) Write a table for decimal to binary converter.

• Ex:- 7 in decimal is 111 in binary.
• 0 in decimal is 000 in binary.

2) Using k-map, we minimize the equation and come with final

equation.
• B0 = D1 + D3 + D5 + D7 + D9;
• B1 = D2 + D3 + D6 + D7;
• B2 = D4 + D5 + D6 + D7;
• B3 = D8 + D9;

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EXTERIOR DESIGN OF DECIMAL TO BINARY
ENCODER
D0 B3
D1

ENCODER
D2 B2

D3

D4

D5
B1
D6

D7
B0
D8

D9

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“4-Bit Carry Look-Ahead Adder (CLA)”
Efficient Addition in Digital Circuits

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Introduction to Carry Look-Ahead Adder

• A fast adder that reduces delay caused by carry propagation.

• Uses a parallel approach to compute carries in advance.
• Improves performance over ripple carry adders.

Key Concepts in CLA

• Propagate (P): Determines if a carry will propagate. P = A XOR B
• Generate (G): Determines if a carry will be generated. G = A AND B
• Carry Out (C): Combines propagate and generate signals.
C(i+1) = G(i) + P(i) * C(i)

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 Carry Look Ahed Adder Block Diagram

Carry prediction

B3 A3 B2 A2 B1 A1 B0 A0

G3 G0
G2 G1
F. A. F. A. F. A. C0 F. A. Cin
C2 C1
P3 P2 P1 P0

S3 S2 S1 S0
Cout

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Carry Propagation And Generation Equations

• C1 = G0 + P0*Cin
• C2 = G1 + P1*C1
= G1 + P1*G0 + P1*P0*Cin
• C3 = G2 + P2*C2
= G2 + P2*G1 + P2*P1*G0 + P2*P1*P0*Cin
• C4 = G3 + P3*C3
= G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*G0 +
P3*P2*P1*P0*Cin

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 Carry-Output-Generation

C4

P3

G3

C3
P2
G2

P1
G1 C2
C1 25
 Carry-Look-ahead-Adder-Truth-Table
A B Ci Ci+1 Condition
0 0 0 0 No carry generate
0 0 1 0 No carry generate
No Carry
0 1 0 0 Generate
No carry generate
0 1 1 1
1 0 0 0
No carry
1 0 1 1 propagate
1 1 0 1
1 1 1 1
Carry generate

It can be observed from the equations and truth table that

carry Ci+1 only depends on the carry C0, not on the
intermediate carry bits.
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Advantages of Carry Look-Ahead Adder
• Reduces carry propagation delay.
• Faster addition for large bit-widths.
• Suitable for high-speed applications.

Application of Carry Look-Ahead Adder

• Used in arithmetic logic units (ALUs).
• Integral part of digital processors.
• Key component in high-performance computing
systems.

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“Flipflop Converter”

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 Flip flop conversions

SR to D

T to D SR to JK

D to SR SR to T
All Possibilities

D to T JK to T

JK to SR JK to D
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 PROCEDURE FOR CONVERSION

Draw the block diagram of the target flipflop from the given problem.

Write Characteristic Table for the target flipflop.

Write excitation table for the available flipflop.

Draw k-map for target flipflop.

Draw the block diagram. (Give Input Pins)

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Ex : JK to D Flip-Flop Conversion

Input Present State Next State Flip Flop Inputs

D Qn Qn+1 J K

0 0 0 0 X

0 1 0 X 1

1 0 1 1 X

1 1 1 X 0

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 K- MAP FOR JK TO D FLIPFLOP

J K
q’(n) q(n) q’(n) q(n)

D’ 0 X D’ X 1
D

D 1 X D X 0

J=D K = D’

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CIRCUIT DIAGRAM

D J Q

CLK
K Q’

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All Other Conversions
Conversion Pins

SR  JK S = Jq’(n) , R = Kq(n)

SR  D S=D , R= D’

SR  T S = Tq’(n) , R = Tq(n)

JK  SR J=S , K=R

JK  D J = D , K = D’

JK  T J=T , K=T

D  JK D = Jq’(n) + K’q(n)

D T D = T + q(n)

T  JK T = Jq’(n) + Kq(n)

T  SR T = Sq’(n) + Rq(n)

T D T = D + q(n)
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 Counters
• A counter is a sequential circuit that counts pulses and produces
a sequences or mod(States).
• Uses
 Frequency Division
 To Count no. of Clock cycle Applied
 Used for Pulse Stretching
• MOD no of Counter
 Total no of Different States in Counter
Ex. 0 – 1 – 4 – 7 – 6 : MOD no. 5
 After Application of MOD no Counter will go to it’s Starting
State.
• Types
1. Asynchronous Counter
2. Synchronous Counter
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MOD of Counter Concept
• Let’s Understand with a Example
• MOD : 0 – 1 – 3 – 2 MOD no :
4
QA QB
• QB • QA
0 0
Ton = 2 clk Ton = 2 clk
0 1 Toff = 2 clk Toff = 2 clk
1 1 TQA = 4 clk TQA = 4 clk
fQB = fclk / 4 fQA = fclk / 4
1 0

Clk

QA

QB 36
What is an Asynchronous Counter?
• The flip-flops are not clocked simultaneously (Different Clocks).
The output of one flip-flop acts as the clock input for the next
flip-flop.
• Execution Slower (why ?)
• Only Fixed Sequence is Possible
• Propagation Delay Accumulated is increase as per going to block.

• Up Sequence
1 Q0 1 Q1 1 Q2 1 Q3
• Down Sequence Possible Sequence
1 Q0’ 1 Q1’ 1 Q2’ 1 Q3’
• BCD counter
CLK

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No. of Flip-Flop are Required for designing a Counter
Mode M Counter  N flip-flop
• Where 2^N >= M
• M is nothing but no of possible states

Ex : counting Sequence
• 0-1-2-3-4-5-6-7 and repeat it
• Than N = 3 that means No of Flip flops are three
• And by the using of we can generate a total 8 mods

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 MOD-16 Counter by Asynchronous
• Let’s Consider a 4bit Asynchronous Counter

1 Q0 1 Q1 1 Q2 1 Q3

1 Q0’ LSB 1 Q1’ 1 Q2’ 1 Q3’ MSB

CLK • Q0 Toggles in every Clock pulses

• Q1 Toggles when Q0 goes from 1  0
• Q2 Toggles when Q1 goes from 1  0
• Q3 Toggles when Q2 goes from 1  0
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Truth Table and Working
Clock Q3 Q2 Q1 Q0 Sequence
1st 0 0 0 0 0
2nd 0 0 0 1 1
3rd 0 0 1 0 2
4th 0 0 1 1 3
5th 0 1 0 0 4
6th 0 1 0 1 5
7th 0 1 1 0 6
8th 0 1 1 1 7
9th 1 0 0 0 8
10th 1 0 0 1 9
11th 1 0 1 0 10
12th 1 0 1 1 11
13th 1 1 0 0 12
14th 1 1 0 1 13
15th 1 1 1 0 14
16th 1 1 1 1 15
0 0 0 0 0

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CLK

Q0

Q1

Q2

Q3

Working of Counter / Wave form Representation 41

Clear and Set Pin
• Clear input or CLR PIN Input
When activated then it will be clear(reset/0) the output
Q of Flip Flop irrespective of i/p Flip Flop and Clock i/p

• Preset input or PRE PIN Input

When Activated then it will be set the output Q of the
irrespective of Flip Flop and clock i/p.

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Max Clock Frequency

1 Q0 1 Q1 1 Q2 1 Q3

1 Q0’ 1 Q1’ 1 Q2’ 1 Q3’

LSB MSB

CLK T(df) T(df) T(df) T(df)

Next Clock must be >= 4T(df)

Than Counter will show a Counting Otherwise it’s not working Properly

So, T(clk) >= NT(df)

where N = no. of Flip flop
⸫ 1/f(clk) >= NT(df)
⸫ f(clk) <= 1/ NT(df) (max clock frequency)
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 Decoding Error

0 0 1 0 1 1

0 0 0 0 1 0
Decoding Error
0 1 0 0 0 0

1 0 0

Decoding Error

• 1 0 1 1  1 1 0 0 : decoding error(1 0 1 0, 1 0 0 0)

44
 How to Avoid Decoding Error

Strobe
1 Q0 1 Q1 1 Q2 1 Q3

1 Q0’ 1 Q1’ 1 Q2’ 1 Q3’

LSB MSB

CLK
T(df) T(df) T(df) T(df)

Ts  timing for Strobe signal is high

For Proper Operation Tclk >= N * T(df) + ts N*tdf ts

45
“Understanding Setup Time and Hold
Time in Digital Circuits"

46
Introduction
• Setup Time:The minimum time before the clock edge that the data input
must remain stable to be reliably captured.
------------------------
-------------------------

Input

CLK
Tset

47
Continue..

• Hold Time:The minimum time after the clock edge that the data
input must remain stable to ensure proper operation.
----------------------------
----------------------------

Input

CLK
THol

48
Why Are They Important?

• Ensure proper data capture in sequential circuits.

• Prevent timing violations like:
• Setup Time Violation: Data changes too late.
• Hold Time Violation : Data changes too early.
• Maintain circuit functionality at desired clock speeds.

49
 Setup Time Violation

• Occurs when data is not stable before the clock edge.

• Leads to incorrect data capture or metastability.

-------------------------
------------------------

Input
Setup
CLK Time
violation

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 Hold Time Violation
• Occurs when data changes too soon after the clock edge.
• Causes incorrect latching of data.
-------------------------
--------------------------
------------------------

Input
Tset
Hold
CLK Time
Violation

51
Design Techniques to Avoid Violations
• Use flip-flops with better timing characteristics.
• Optimize clock distribution networks.
• Insert buffers to manage propagation delays.
• Adjust clock frequency for safe operation.

52
“Glitches and Hazards”

53
Glitches And Hazards
Definition
• A glitch is a short-lived, unintended pulse in a digital circuit's output.
• It occurs during signal transitions due to varying delays in the circuit.
Key Points
• Glitches appear as switching transients in combinational outputs.
• They result from propagation delays across different paths.
Causes of Glitches
1.Propagation delays in logic gates.
2.Unequal delays in input signal paths.
3.Race conditions during state transitions.

54
Types of Glitches
Static-1 glitch: The output should remain at logic 1 but temporarily
dips to logic 0.

Static-0 glitch: The output should remain at logic 0 but temporarily

spikes to logic 1.

Dynamic glitch: The output may transition multiple times before

settling.

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Elimination of Hazards
Method-1
• Since Unequal delays are the main cause of Hazards,
Adding buffer to balance delays in parallel path can
eliminate hazard.

2ns 2ns
A 2ns A 2ns
B B
f f
C C
1ns 1ns

56
Method-2
• Adding Redundant gates can eliminate Hazards.
• The additional AC path acts as a "safety net," ensuring the
output doesn't glitch during specific transitions.

• f = Σm(3,4,5,7)
A
BC
A 00 01 11 10 F
0 0 B
0 1 0
C
1 1 1 1 0

F’= AB’ + BC + AC A

57
Method-3
• Adding pipelining registers at the end of combinational
circuit.
2ns
A 2ns f
B D Q Y
C
Clk

Clk

Y
58
“Shift Register”

59
 A Shift Register is a sequential logic circuit used to store
Intoducion of Shift Register
and shift data.

 Data is moved bit by bit through flip-flops in response to

clock pulses. Parallel Parallel
input output
 It shifts data left or right based on control signals.

 Widely used for data storage and transfer in digital

Serial
systems. Serial N bit shift
output
input register
Classification of Register
 serial-In, Serial-Out (SISO): Data enters/exits one bit at
a time.
 Serial-In, Parallel-Out (SIPO): Data enters serially, exits Clock
in parallel.
 Parallel-In, Serial-Out (PISO): Data enters in parallel,
Timing and Control
exits serially.
Parallel-In,
 Clock Input: Synchronizes
Parallel-Out bit shifting.
(PIPO): Data enters/exits in
parallel.
Control Signals: Manage shifting (e.g., enable/reset)

60
 SISO (Serial-In Serial-Out)

Introduction
 A Serial-In Serial-Out (SISO) Shift Register is a type of
sequential circuit used to store and transfer data bit by bit.

Key Features
 Data enters the register serially bit by bit and exits serially after
being shifted through all stages.

Data In Data Out

A. Serial-In Serial-Out
61
 Structure
 Flip-flops connected in series with one serial input and
one serial output, controlled by a shared clock.
Working
 Initialization: Data enters serially, bit by bit.
 Shifting: Each clock pulse moves data to the next flip-
flop.
 Output: Data appears at the output after N clock cycles.

Serial Serial
D Q3 D Q2 D Q1 D Q0
DataIn DataOut
clk clk clk clk

clock

62
How Shifting Occurs in SISO Shift
Registers

Initialization: Load a 4-bit sequence (e.g., "1010") one bit at a

time via the serial input.
Clock Pulses: Each pulse shifts data right. The first flip-flop
Ex. is the current bit.
receives the new bit, and the last outputs
Example Shifting: 0101
Clock Q3 Q2 Q1 Q0
Pulse 1: “0---"
0 0 0 0 0
Pulse 2: “01--"
Pulse 3: "010-" 1 1 0 0 0
Pulse 4:
 Output: "0101"
Bits exit sequentially 1 0 1 0 0
from the last flip-flop 1 1 0 1 0
1 0 1 0 1

63
64
 SIPO (Serial-In Parallel-Out)
Definition
A SIPO Shift Register takes serial data input and provides
parallel output after processing.

Key Features
Shifts data serially, one bit per clock pulse.
Outputs all data in parallel after N clock cycles for an N-bit
register.

Data Out

Data In

B. Serial-In Parallel-Out 65
Structure
 Flip-flops connected in series with one serial input, multiple
parallel outputs, and a shared clock for synchronization.
Working
 Bits enter serially through the input line.
 Each bit is stored in a flip-flop and shifted to the next stage on
every clock pulse.
 The full data word is available simultaneously at the parallel
output lines. Data Out
DQ3 DQ1 DQ1 DQ0
Data Input D Q3 D Q2 D Q1 D Q0

clk clk clk clk

clock
clear

66
67
 PISO(Parallel-In Serial-Out)
Definition
 A Parallel-In Serial-Out (PISO) Shift Register is
used to load parallel data and shift it out serially,
bit by bit. Data In
 It’s designed for parallel-to-serial conversion,
enabling efficient data transfer.

Key Features Data Out

 Converts parallel data to a serial stream.
 Synchronization is achieved using a clock signal. C. Parallel-In Serial-Out

68
Structure
 Flip-flops store data, multiplexers handle serial shifting and
Parallel inputs allow simultaneous data loading.

Working Mechanism
 Parallel Load: Data is loaded simultaneously into flip-flops.
 Shifting: Bits shift one position per clock pulse.
 Serial Output: Outputs one bit per cycle until all bits are
shifted out.

69
 ParalleI Input

Control
Signal

AND AND AND AND AND AND

OR OR OR

Serial
D Q3 D Q2 D Q1 D Q0
out
clk clk clk clk

clock
clear
70
71
 PIPO(Parallel-In Parallel-Out)

Definition Data In
 A Parallel-In Parallel-Out (PIPO) Shift
Register accepts and outputs data in
parallel without serialization.
 It’s primarily used for fast data
storage and transfer.

Key Features
 Operates on the entire data word at Data Out
once. D. Parallel-In Parallel-Out
 No shifting occurs; only storage and
transfer functions are performed.
72
Structure
 Consists of flip-flops with parallel input and parallel output connections.
 All bits are loaded and retrieved simultaneously.
Working Mechanism
 Parallel Load: Data is loaded into all flip-flops at the same time.
 Parallel Output: All bits appear simultaneously at the output lines.

Parallel DataOut

QA QB QC QD

D Q3 D Q2 D Q1 D Q0

clk clk clk clk

clock
PA PB PC PD
Parallel Data In73
74
 Bidirectional Shift Register
Definition
 Sequential circuit for storing and shifting
data.
 Uses flip-flops to move data bit by bit.
 Shifts data left or right with control
signals.
Structure
 Enables flexible and reversible data Working
Flip-Flops:
operations.Store data. Data Input: Entered serially.
Clock Input: Synchronizes shifts. Direction Control:
Control Signals: Select direction (left  Left Shift: Data moves to higher-order
or right). bits.
Serial Data I/O: For data entry and  Right Shift: Data moves to lower-
retrieval. order bits.
Direction Logic: Manages bidirectional Clock Pulse: Shifts data through flip-
flow. flops.
Data Output: Exits serially at the
output. 75
Control
Signal

Dr Dl
AND AND AND AND AND AND AND AND

OR OR OR OR

D Q3 D Q2 D Q1 D Q0

clk clk clk clk

clock
clear
76
77
 FIFO(First-In First-Out)
What is FIFO?
 FIFO (First-In, First-Out) is a sequential
data storage and transfer system where the
first data input is the first to be output.
 Operates like a queue, maintaining the order
of data flow.

Key Features data written

data read
from FIFO
 Ensures order preservation: Data exits in in FIFO

the same order it enters.

 Commonly used for data buffering,
synchronization, and interfacing.

78
 Structure of FIFO
Components
Wr_Clk Rd_Clk
• Input/Write Port: Accepts new data.
Data_In Data_out
• Flip-Flops: Temporarily store data sequentially.
Wr_en
FIFO Rd_in
• Output/Read Port: Retrieves data in the same order as entered.
Full Empty
• Control Logic: Manages read/write operations and data flow.
How It Works
• Data enters through the write port and shifts toward the read port. Rst

• Control signals (e.g., enable, full/empty flags) regulate data entry and output.
Types of FIFO
Synchronous FIFO Asynchronous FIFO
 Both read and write operations are clocked  Read and write operations use different
by the same clock signal. clock signals.
 Used when the input and output operate at  Ideal for systems with mismatched
the same speed. input/output speeds.

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80
 Usage of shift registers

SISO (Serial-In Serial-Out) PISO (Parallel-In Serial-

 Transfers data bit by bit over a Out)
single line.  Combines parallel data into a
serial stream for
 Useful for signal delay and
transmission.
temporary data storage.  Optimizes microcontroller I/O
usage and data compression.
SIPO (Serial-In Parallel-Out)
 Converts serial data into PIPO (Parallel-In Parallel-
parallel for processing. Out)
 Common in interfacing and  Holds entire data words for
driving multiple LEDs. temporary storage.
 Enables fast parallel data
transfer between systems.
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FIFO (First-In First-Out)
 Buffers data for speed mismatch resolution in communication
systems (e.g., UART, Ethernet).
 Ensures smooth data flow in pipelines or processors.
 Temporarily stores data between sender and receiver.

Bidirectional Shift Register

 Reversible data shifting for advanced operations.
 Useful in digital filters, signal routing, and bit manipulation.
 Transfers data between registers in multi-directional systems.

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“Memories”

83
What is Memory?
• Memory devices store data temporarily or permanently.
• Used in digital systems like computers and hard disks to store user data or
control programs.
• To handle large data efficiently, memory devices must have high capacity
and be cost-effective.
Block diagram : Data lines

Address lines

Memory unit
Read

Write
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Structure and Operations of Memory

Registers and Cells

• Registers form the fundamental units of memory.
• Each register comprises cells, storing one bit per cell.
Address and Capacity
• Memory locations are defined by unique addresses.
• Capacity represents the total bits a memory unit can hold.
Write & Read Operations
• Data transfer is facilitated via control, address, and data lines.

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 CLassification

Memory

Volatile Non-volatile
Memory Memory

Flash
SRA DRA RO PRO EPRO EEPRO
memor FRAM MRAM
M M M M M M
y

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Volatile memory
• Volatile memory is a type of computer memory that
requires a continuous power supply to retain data.
• All data is lost when the power is turned off.
• Used for temporary storage and high-speed
operations.

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Types of Volatile Memory
Static RAM (SRAM)
• Stores data using flip-flops.
• Faster and more reliable than DRAM.
• Used in cache memory.
Dynamic RAM (DRAM)
• Stores data using capacitors.
• Requires periodic refreshing to retain data.
• Used as main memory in computers.

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Non-Volatile Memory
• Non-volatile memory is a type of memory that retains
data even when the power is turned off.
• It is used for long-term data storage in digital devices.

89
Types of Non-Volatile Memory
Read-Only Memory (ROM)
• Permanently stores system firmware.
• Variants:
• PROM: Can be programmed once.
• EPROM: Erased with UV light and reprogrammed.
• EEPROM: Erased and rewritten electrically.

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Continue...

Flash Memory
• High-speed, rewritable memory.
• Used in USB drives, SSDs, and memory cards.
Magnetoresistive RAM (MRAM)
• Combines non-volatility with high speed.
• Stores data using magnetic elements.
Ferroelectric RAM (FRAM)
• Uses ferroelectric material for durability and efficiency.

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“Programmable Logic Device”

92
What is Programmable Logic Device (PLD)?

• Used for designing digital logic circuits.

• Configurable by users after manufacturing.

• Contains programmable AND-OR gate arrays.

• Connections between inputs and outputs are user-defined.

93
 Types of PLD’s
• Simple PLDs: PAL, PLA, PROM.

• Complex PLDs: CPLD (Complex PLD), FPGA (Field

Programmable Gate Array).

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 PAL (Programmable Array Logic)
• It is PLD with a programmable AND array and a fixed OR array.

• The AND array performs the necessary logic functions, while the OR
• Array allows custom combinations of those functions.

OUTPUTS
INPUTS

PROGRAMM
FIXED OR
ABLE AND
ARRAY
ARRAY

95
“Implementation Of Full Adder Using PAL”

96
 Truth Table and Boolean Eq. of Full Adder
A B C S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

• Using K-map we will get the boolean equation for Sum

& Cout
• Sum = A’B’C + A’BC’ + AB’C’ + ABC
• Cout = BC + AB + AC 97
 Diagram
A B C

SUM

CARRY

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“Programmable Logic Array”

99
 PLA (Programmable Logic Array)
• A PLD with programmable AND and OR arrays.

• PLA is more versatile compared to PAL due to its dual programmability.

OUTPUTS
INPUTS

PROGRAMM PROGRAMM
ABLE AND ABLE OR
ARRAY ARRAY

100
“Implementation Of Full Adder Using PLA”

101
 Truth Table and Boolean Eq. of Full Adder
A B C S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

• Using K-map we will get the boolean equation for Sum &
Cout
• Sum = A’B’C + A’BC’ + AB’C’ + ABC
• Cout = BC + AB + AC
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 Diagram
A B C

SUM CARRY
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“Programmable Read Only Memory”

104
 PROM (Programmable Read Only Memory)
• It has a fixed AND array (decoder) and a programmable OR array.

• Limited flexibility compared to PLA because the AND array is

fixed.

OUTPUTS
INPUTS

FIXED AND
PROGRAMMA
ARRAY
BLE OR ARRAY
(DECODER)

105
“Implementation Of Full Adder Using PROM”

106
 Truth Table of Full Adder
A B C S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

• Sum = S =Σm(1,2,4,7)
• Cout = Σm(3,5,6,7)
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 Diagram

Y0
A Y1
3X8 Y2
B Y3
DECODER Y4
Y5
C Y6
Y7

SUM CARRY

108
What is CMOS ?

109
CMOS (Complementary Metal-Oxide-
Semiconductor)
It is a technology used to design digital and analog circuits
CMOS circuits use:
•PMOS Transistors: Operate when input is LOW (0).
•NMOS Transistors: Operate when input is HIGH (1).

NMOS PMOS

G G
B S D S D B

P+ n+ n+ P+ P+ n+

n-well
P substrate
110
“NAND Gate using CMOS”

111
 VDD
NAND Gate: Outputs LOW only when all
inputs are HIGH
Logic Equation: Y= A⋅B

A B • Two PMOS transistors in parallel

connected to VDD
• Two NMOS transistors in series
connected to GND.
Y Operation:
•At least one input LOW → PMOS ON →
A Y=1 (HIGH).
•Both inputs HIGH → NMOS ON → Y=0
(LOW).
A B Y
B 0 0 0
0 1 1
1 0 1
1 1 1 112
“NOR Gate using CMOS”

113
 VDD NOR Gate: Outputs HIGH only when all
inputs are LOW.
Logic Equation: Y= A+ B
A Two PMOS transistors in series
connected to VDD
Two NMOS transistors in parallel
connected to GND
B •Operation:
•Both inputs LOW → PMOS ON →
YY=1(HIGH).
•At least one input HIGH → NMOS ON →
Y=0(LOW).
A B Y
A B
0 0 1
0 1 0
1 0 0
1 1 0
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Reference
https://www.tutorialspoint.com/digital-electronics/im
plementation-of-nand-nor-gate-using-cmos.htm
https://www.elprocus.com/carry-look-ahead-adder/

https://en.wikipedia.org/wiki/CMOS

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