Scribd
Upload
10 views

Verilog _introduction _1_ (1)

The document provides an introduction to Verilog HDL, a hardware description language used in VLSI design, highlighting its syntax similarities to C, case sensitivity, and various abstraction levels such as circuit, gate, data flow, and behavioral levels. It discusses the design flow, including simulation, synthesis, and functional verification, as well as the structure of Verilog modules, ports, and the use of wire and reg elements. Additionally, it covers test bench syntax and language constructs, including case sensitivity and number expression formats.

Uploaded by

cbjr0096
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
10 views

Verilog _introduction _1_ (1)

The document provides an introduction to Verilog HDL, a hardware description language used in VLSI design, highlighting its syntax similarities to C, case sensitivity, and various abstraction levels such as circuit, gate, data flow, and behavioral levels. It discusses the design flow, including simulation, synthesis, and functional verification, as well as the structure of Verilog modules, ports, and the use of wire and reg elements. Additionally, it covers test bench syntax and language constructs, including case sensitivity and number expression formats.

Uploaded by

cbjr0096
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 26

Verilog introduction

VLSI design flow


VLSI design flow
HDL

• Verilog HDL is a general purpose hardware description language that


is easy to learn and easy to use.
• It is similar in syntax to c programming language
• Verilog is a case sensitive language
• The engineer can describe the hardware in terms of
switches,gates,RTL behavioral model
Circuit Level or switch level
• At the circuit level, a switch is the basic element with which digital
circuits are built.
• Switches can be combined to form inverters and other gates at the
next higher level of abstraction
Gate Level

• At the next higher level of abstraction, design is carried out in terms


of basic gates.
• All the basic gates are available as ready modules called “Primitives”.
• Data Flow
• Data flow is the next higher level of abstraction.
• All possible operations on signals and variables are
represented here in terms of assignments
y = (ab+cd)
• Behavioral Level
• Behavioral level constitutes the highest level of design
description; it is essentially at the system level itself. 
• With the assignment possibilities, looping constructs and
conditional branching possible, the design description
essentially looks like a “C” program.
Simulation and Synthesis
• The design that is specified and entered as described earlier is simulated for
functionality and fully debugged.
• Translation of the debugged design into the corresponding hardware circuit
(using an FPGA or an ASIC) is called “synthesis.”
• The circuits realized from them are essentially direct translations of functions
into circuit elements.
• Functional Verification
• Testing is an essential ingredient of the VLSI design process as with any
hardware circuit.
• It has two dimensions to it – functional tests and timing tests.
• Testing or functional verification is carried out by setting up a “test bench” for
the design.
MODULE
• Any Verilog program begins with a keyword – called a “module.”
• A module is the name given to any system considering it as a black
box with input and output terminals as shown in Figure 
• The terminals of the module are referred to as ‘ports’.
Defining a module
Ports
• The ports attached to a module can be of three types:
• input ports through which one gets entry into the module  output
ports through which one exits the module.
• inout ports: These represent ports through which one gets entry into
the module or exits the module
• All the constructs in Verilog are centered on the module.
Module syntax
• module module_name (port_list);
• Input, output, inout declaration
• Intermediate variable declarations
• Functional Description (gate / switch / data flow /
Behv.)
• endmodule
wire and reg
• wire elements are used to connect input and output ports of a
module instantiation together with some other element in your
design.
• wire elements are used as inputs and outputs within an actual
module declaration
• wire elements must be driven by something, and cannot store a value
without being driven.
• wire elements cannot be used as the left-hand side of an = or <= sign
in an always@ block.
• wire elements are the only legal type on the left-hand side of an
assign statement
Wire and reg
• reg are similar to wires, but can be used to store information (‘state’)
like registers.
• reg elements can be used as outputs within an actual module
declaration.
• reg elements cannot be used as inputs within an actual module
declaration.
• reg is the only legal type on the left-hand side of an always@ block =
or <= sign.
• reg is the only legal type on the left-hand side of an initial block = sign
(used in Test Benches).
• reg cannot be used on the left-hand side of an assign statement.
• TEST BENCH SYNTAX  A test bench is HDL code that allows you to
provide a documented, repeatable set of stimuli.
• module tb_module_name ;
• Input, output, inout declaration
• Intermediate variable declarations
• Stimulus (initial / always)
• endmodule
LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG

• CASE SENSITIVITY Verilog is a case-sensitive language like C


• KEYWORDS The keywords define the language constructs.
• A keyword signifies an activity to be carried out, initiated, or
terminated
• All keywords in Verilog are in small letters
How to express numbers
• N’Bxx
• (N) Number of bits :Expresses how many bits will be used to store the
value
• (B) Base :Can be b (binary), h (hexadecimal), d (decimal), o (octal)
• (xx) Number : The value expressed in base, apart from numbers it can
also have X and Z as values.
And gate design using verilog
2 x 1mux verilog code
3x8 Decoder using behavioral
modelling
3x 8 decoder using dataflow model

You might also like