DFT BASICS

What is DFT?
 Definition : Dft is a methodology or collection of
methodologies, which results in creation of testable design.
 What is testability or testable design?
a design is said to be testable, if all internal nodes of interest
are simultaneously controllable and observable.
 What is controllability?
ability to set some circuit nodes to certain states or logic
values
 What is observability?
ability to observe states or logic values of internal nodes
Why DFT
Dft is a technique, which facilitates a design
to become testable after production.
To detect manufacturing defects.
To improve test quality.
To reduce test cost.
To reduce debug time.
DFT FLOW
Structural testing
DFT flow in scan level:
1. Scan insertion.
2. Scan compression.
3. Atpg.
4. Simulation.
1.SCAN INSERTION
 What is scan?
Scan is a technique, used for converting a difficult to test
a sequential design into easy to test a combinational
design. And it facilitates controllability and observability of
each and every node in a design.
 What is scan insertion?
The functional D flip flop is converted into scan D flip flop,
by keeping multiplexer (2*1) at the input of the D flip flop.
 What is scan chain?
stitching of scan flops is called scan chain.
 Why scan?
To improve design testability. once scan inserted, the atpg
tool will be able to generate patterns that achieve high
test coverage.
INPUTS AND OUTPUTS OF SCAN
Inputs:
Gate level netlist.
Libraries.
Number of scan inputs and outputs.
Compression ratio.
CTL.
Path hierarchy for security logic.
Outputs:
Scan inserted netlist.
Test procedure file.
Atpg set_up file
SCAN INSERTION FLOW
There are several steps in scan insertion flow:
 Invoke tool
 Read net list and libraries.
 Set current design and Link library.
 Set scan architecture and convert to scan.
 Define clocks, resets and their off-state values.
 Define Test Mode.
 Create port and define created ports.
 Define scan configuration .
 Create test-protocol.
 Run drc and fix drc’s .
 Scan stitching.
 Write netlist and reports.
2.SCAN COMPRESSION
What is compression?
Compression is a technique of adding some
additional on-chip hardware before the scan
chains to decompress the test stimulus coming
from the ATE and after the scan chains to
compress the response going to the ATE.
Why compression?
Compression is a technique, which is used to
reduce the test time, test cost and test data
volume.
EDT DESIGN
A. DECOMPRESSOR
Decompressor is located between scan
channel inputs and internal scan chain inputs.
Which is used to decompress the external
channels into number of internal scan chains.
Decompressor consists of
1. Linear feedback shift register(LFSR): which
is used for generating random test patterns
from one test pattern.
2. Phase shifter: it is a ex-or logic , used for
blocking repeated patterns generated by
LFSR.
B. COMPACTOR
 Compactor is Located between internal scan chain
outputs and external channel outputs.
 Which is used to compress the number of internal scan
chains into external scan channels.
 Compactor consists of
1. Ex-or logic: which is used to compress the test data
output of internal scan chains and fed to external
channels.
2. Mask logic: which is used for masking X value and to
avoid aliasing effect. Mask logic consists of
 Mask shift register.
 Mask hold register.
 Decoder.
INPUTS AND OUTPUTS OF SCAN
COMPRESSION
Inputs:
Scan inserted netlist.
Library.
Edt.rtl file
Outputs:
Edt inserted netlist.
Edt do file.
Edt test procedure file(test proc file).
Edt bypass file.
Edt bypass test proc file.
Synthesis script..
FORMULAS OF COMPRESSION
Compression ratio: it is defined as the ratio of
internal scan chains to external channels.
Test time: number of patterns * maximum
chain length * time period of clock cycle.
Test data volume: number of patterns *
maximum chain length * external channels.
Maximum chain length: it is defined as the
ratio of total flops to the internal scan chains.
3.AUTOMATIC TEST PATTERN
GENERATION(ATPG)
Definition:
Test patterns are also called as test vectors,
are set of 1’s and 0’s placed on primary input
pins during manufacturing test process to
determine, if the chip is functioning properly.
When the test pattern is applied, ATE
determines if the chip is free from
manufacturing defects by comparing fault
free output with the actual output.
4. SIMULATION
 Definition: Imitative representation of the functionality of circuits
in alternative method, a computer program say, is called
simulation.
 Fault simulation: A technique to determine faults covered by
random patterns called fault simulation.
 Process: Applying random patterns and comparing the actual
response of the circuit with the fault-free response of the same. If
mismatch between these two responses then circuit is faulty, else
circuit is said to be fault-free. In that way faults are detected by
random patterns.
 Simulations are two types
 Serial simulation.
 Parallel simulation.
FAULT MODELS
Different Manufacturing defects are replaced
by different fault models for ease of creating
test patterns to detect them.
There are four types of fault models:
1. Stuck at fault model.
2. Delay fault model.
3. Bridging fault model.
4. IDDQ fault model.
1.STUCK AT FAULT MODEL
There are two types in stuck at fault model.
Functional testing is used to detect these
faults.
 Stuck at 0.
 Stuck at 1.
2.DELAY FAULT MODEL
There are two types in at-speed faults. To
detect these faults at-speed testing is used.
A. Transition delay faults:
 Slow to rise.
 Slow to fall.
B. Path delay faults.
 Slow to rise.
 Slow to fall.
3.BRIDGING FAULT MODEL
There are two types in this fault model.
Functional testing is used to detect these
faults.
 AND bridging.
 OR bridging.
3. IDDQ FAULT MODEL
IDDQ fault model detects all defects by
transistor based fault model, mainly for
CMOS stuck-on defect.
IDDQ testing is used to detect IDDQ fault
model.
In IDDQ testing, tool monitors current for
every vector in the test. And also used for
transistor leakage fault model.