University of Bahrain

College of Information Technology

Department of Computer Science

Dr. Abdul Fattah Salman

ITCS 222: Computer Organization

Decoders, Encoders, and Multiplexers

 ITCS 222: Computer Organization

These slides are based on slides of Prof.

Muhamed Mudawar (KFUPM) and modified
by Dr. Abdul Fattah Salman
 Functional Blocks
• Functional blocks are the building blocks used in designing
digital systems and computers
• A functional block is a combinational circuit and we will
study the most common functional blocks: such as encoders,
decoders, multiplexers, etc.
• In the past, functional blocks were integrated circuits
SSI: Small Scale Integration = tens of gates
MSI: Medium Scale Integration = hundreds of gates
LSI: Large Scale Integration = thousands of gates
• Today, functional blocks are part of a design library
• Tested for correctness and reused in many projects
ITCS 222– Computer Organization slide #3 Decoders, Encoders, and Multiplexers
 Binary Decoders
• Given a n-bit binary code, there are 2n possible code values
• A binary decoder is a combinational circuit that converts a n-
bit code at its input to one of its 2n output.
• The decoder has an output for each possible code value
• The n-to-2n decoder has n inputs and 2n outputs
• Depending on the input code, only one output is set to logic 1
• The conversion of n-bit input to one of 2n output is called
decoding

A decoder can have

2n outputs

n – to - 2n less than 2n outputs

inputs

Decoder
if some input codes




are unused
n

ITCS 222– Computer Organization slide #4 Decoders, Encoders, and Multiplexers

 Examples of Binary Decoders
Input
d0
Outputs
s

a1 2-to-4 d1

4 Outputs
a1 a0 d0 d1 d2 d3
2 Inputs

a0 d2
Decoder
0 0 1 0 0 0 Truth
d3
0 1 0 1 0 0
Tables
1 0 0 0 1 0
1 1 0 0 0 1

d0
Inputs Outputs

d1
a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7

d2
a2
0 0

3-to-8 d3
1 0 0 0 0 0 0 0
8 Outputs

0
a1
3 Inputs

d4
0 0

a0 Decoder
0 1 0 0 0 0 0 0
1
d5
0 1

d6
0 0 1 0 0 0 0 0
0

d7
0 1
0 0 0 1 0 0 0 0
1
1 0
0 0 0 0 1 0 0 0
0
ITCS 222– Computer Organization slide1#5 0 Decoders, Encoders, and Multiplexers
0 0 0 0 0 1 0 0
 Decoder Implementation
2-to-4 Decoder 3-to-8 Decoder

Inputs Outputs
𝑎2
a1 a 0 d0 d1 d2 d3 𝑎1
′ ′ ′
0 0 1 0 0 0 𝑎0 𝑑0 =𝑎2 𝑎1 𝑎0
0 1 0 1 0 0 ′ ′
1 0 0 0 1 0 𝑑1=𝑎2 𝑎1 𝑎0
′ ❑ ′
1 1 0 0 0 1
𝑑2 =𝑎2 𝑎1 𝑎0
𝑎1 ′ ❑
𝑑3 =𝑎2 𝑎1 𝑎0
𝑎0 ❑ ′ ′
𝑑 4=𝑎2 𝑎1 𝑎0
′
𝑑1=𝑎1 𝑎 0 ❑ ′
′ 𝑑5 =𝑎2 𝑎1 𝑎0
𝑑2 =𝑎1 𝑎 0 ❑ ❑ ′
𝑑3 =𝑎1 𝑎0 𝑑6 =𝑎2 𝑎1 𝑎0
❑ ❑
𝑑7 =𝑎2 𝑎1 𝑎0
Each decoder output is a minterm
ITCS 222– Computer Organization slide #6 Decoders, Encoders, and Multiplexers
 Using Decoders to implement Functions
• A decoder generates all possible minterms over the inputs
• A Boolean function can be expressed as a sum of minterms
• Any function can be implemented using a decoder + OR
gate
Note: the function must NOT be minimized

d0
• Example:
Inputs Full Adder sum = ∑(1, 2, 4, 7), cout = ∑(3, 5, 6, 7)
Outputs

d1
sum
a b c cout sum
d2
a 22
0 0 0 0 0

3-to-8 d3
b
0 0 1 0 1
21
d
0 1 0 0 1
c 20 Decoder 4 cout
d5
0 1 1 1 0

d6
1 0 0 0 1
1 0 1 1 0
d7
1 1 0 1 0
1 1 1 1 1
ITCS 222– Computer Organization slide #7 Decoders, Encoders, and Multiplexers
 Using Decoders to implement Functions
• Good if many output functions of the same input variables
• If number of minterms is large  Wider OR gate is needed
• Use NOR gate if number of maxterms is less than minterms
• Example: f = ∑(2, 5, 6), g = ∏(3, 6)  g' = ∑(3, 6), h = ∑(0, 5)
Inputs Outputs
a b c f g h
d0
d1 f
0 0 0 0 1 1
0 0 1 0 1 0 d2
a 22
0 1 0 1 1 0 3-to-8 d3
b 21 g
0 1 1 0 0 0 d
c 20 Decoder 4
1 0 0 0 1 0 d5
1 0 1 1 1 1 d6 h
1 1 0 1 0 0 d7
1 1 1 0 1 0

ITCS 222– Computer Organization slide #8 Decoders, Encoders, and Multiplexers

 2-to-4 Decoder with Enable Input

d0
Truth Table
a1
2-to-4 d1
a0 d2
Inputs Outputs
Decoder
EN d3
EN a1 a0 d0 d1 d2 d3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0 𝒂𝟏
′ ′
1 1 0 0 0 1 0
𝒂𝟎 𝒅 𝟎=𝑬𝑵 𝒂𝟏 𝒂𝟎
1 1 1 0 0 0 1 ′
𝒅𝟏 =𝑬𝑵 𝒂 𝟏 𝒂𝟎
′
𝒅𝟐 =𝑬𝑵 𝒂 𝟏 𝒂𝟎
If EN input is zero then all
outputs are zeros, regardless
𝒅𝟑 =𝑬𝑵 𝒂 𝟏 𝒂𝟎
of a1 and a0 𝑬𝑵
ITCS 222– Computer Organization slide #9 Decoders, Encoders, and Multiplexers
 Building Larger Decoders
• Larger decoders can be built hierarchically using smaller ones
• Example: A 3-to-8 decoder can be built using two 2-to-4 decoders
with Enable input and an inverter (1-to-2 decoder)

a2
d0
Inputs Outputs
a1 a1 Top
d1
a0 a0
a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7

d2
0 2-to-4
Decoder
d3
0 1 0 0 0 0 0 0 0
EN
0
0
0 0 1 0 0 0 0 0 0

1-to-2 Decoder
1

d4
1

a1
0 0 0 1 0 0 0 0 0

d5
0
Bottom
a0
1

d6
2-to-4
0 0 0 0 1 0 0 0 0
1
Decoder
d7
0
EN
1 0 0 0 0 1 0 0 0
0
0
1 0 0 0 0 0 1 0 0
1
ITCS1222– Computer Organization slide #10 Decoders, Encoders, and Multiplexers
 Building Larger Decoders

a1 a1 2-to-4 d0
d1
Example: A 4-to-16
a0 a0Decoder d2
1 d3
decoder with enable can
EN

d4
be built using five 2-to-4
a1 2-to-4
d5
a0Decoder
decoders with enables
d6
a3 a1 2-to-4 EN 2 d7
a2 a0Decoder
a1 2-to-4 d8
EN EN 0 d9
a0Decoder d10
EN 3 d11

a1 2-to-4 d12
d13
a0Decoder d14
Larger decoders can be built
hierarchically in a similar way
EN 4 d15

ITCS 222– Computer Organization slide #11 Decoders, Encoders, and Multiplexers
 Encoders
• An encoder performs the opposite operation of a decoder
• An encoder is a combinational circuit that converts a 2n code
at its input to an n-bit code at its output.
 Typically, one input should be 1 and all others must be 0's

 The output indicates which input is active (logic 1)

• This conversion of input to output is called encoding

n Outputs
An encoder can have less 2n Inputs 2n to n
Encoder


than 2n inputs if some 
input lines are unused
ITCS 222– Computer Organization slide #12 Decoders, Encoders, and Multiplexers
 Example of an 8-to-3 Binary Encoder
• 8 inputs, 3 outputs, only one input is 1 (active), all others are
0's (inactive)
• Encoder generates the output binary code for the active input
• Output is not specified if more than one input is 1

d7
Inputs Outputs

d6
d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0

d5 8-to-3 a2
0 0 0 0 0 0 0 1 0 0 0

d4
3 Outputs

a1
0 0 0 0 0 0 1 0 0 0 1
8 Inputs

d3 Binary
a0
0 0 0 0 0 1 0 0 0 1 0

d2
Encoder
0 0 0 0 1 0 0 0 0 1 1

d1
0 0 0 1 0 0 0 0 1 0 0

d0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

ITCS 222– Computer Organization slide #13 Decoders, Encoders, and Multiplexers
 8-to-3 Binary Encoder Implementation
d7
d6
d5 8-to-3
Inputs Outputs

a2
d4 a1
Binary
d7 d6 d5 d4 d3 d2 d1 d0 a 2 a 1 a 0

d3 a0
d2
0 0 0 0 0 0 0 1 0 0 0

d1 Encoder
0 0 0 0 0 0 1 0 0 0 1

d0
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1

d4
0 0 0 1 0 0 0 0 1 0 0

d5
a2
0 0 1 0 0 0 0 0 1 0 1
d6
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1 d7
d2
d3
d6 a1
a2 = d4 + d5 + d6 + d7
d7
a1 = d2 + d3 + d6 + d7
d1
8-to-3 binary encoder

d
a0
implemented using
a0 = d1 + d3 + d5 + d7 three 4-input OR gates d3
d7
5

ITCS 222– Computer Organization slide #14 Decoders, Encoders, and Multiplexers
 Binary Encoder Limitations
• Exactly one input must be 1 at a time (all others must be 0's)
 If more than one input is 1 then the output will be incorrect
 For example, in the 8-3-encoder:
a2 = d4 + d5 + d6 + d7
 if d3 = d6 = 1, then
a1 = d2 + d3 + d6 + d7
a2 a1 a0 = 111 (incorrect)
a0 = d1 + d3 + d5 + d7

• Two problems to resolve:

1) If two or more inputs are 1 at the same time, what should be the
output?
2) If all inputs are 0's, what should be the output?
Solution:
The output a2 a1 a0 is 000 if d0 is 1 or all inputs are 0's
How to resolve this ambiguity? Use priority encoder!!!
ITCS 222– Computer Organization slide #15 Decoders, Encoders, and Multiplexers
 Priority Encoder
• Priority Encoder solves both problems of the binary encoder
• The 1st problem is solved by assigning priorities to inputs
 If more than one input is active (logic 1) then the input with higher
number is encoded and generates the correct output code.

• The 2nd problem is solved by adding a new output V (Valid)

 The value of output V will be zero, if all inputs are zeros.
d3
a1
highest priority
d2 4-to-2
Inputs Outputs

Priority a0
d1
d3 d2 d1 d0 a1 a0 V

d0 Encoder
lowest priority V
0 0 0 0 X X 0
0 0 0 1 0 0 1

Condensed Truth Table:

0 0 1 X 0 1 1

All 16 cases are listed

0 1 X X 1 0 1
1 X X X 1 1 1

ITCS 222– Computer Organization slide #16 Decoders, Encoders, and Multiplexers
 Implementing a 4-to-2 Priority Encoder

Inputs Outputs 𝑑1 𝑑 0 K-Map of 𝑑1 𝑑 0 K-Map of

d3 d2 d1 d0 a 1 a0 V
𝑑3 𝑑2 00 01 11 10 𝑑3 𝑑2 00 01 11 10
00 X 00 X 1 1
0 0 0 0 X X 0
0 0 0 1 0 0 1 01 1 1 1 1 01
0 0 1 X 0 1 1
1 1 1 1 1 1 1 1 1 1
0 1 X X 1 0 1
1 1
1 X X X 1 1 1 10 1 1 1 1 10 1 1 1 1

d3

Output Expressions:
a1
d2

a0
d1

V
d0

ITCS 222– Computer Organization slide #17 Decoders, Encoders, and Multiplexers
 Multiplexers
• In digital systems, selecting data is an essential function
• A functional block (combinational circuit) that performs selection
operation is called multiplexer.
• A Multiplexer (or MUX) is a combinational circuit that has:
 Multiple data inputs (typically 2n, where n = 1,2,3,… ) to select from
 One output Y d0

2n Inputs
 An n-bit select input S used for control d1
d2

Mux
. Y
.
.
d2n–1
n
S

• The n-bit select input defines which data input is passed to the output
ITCS 222– Computer Organization slide #18 Decoders, Encoders, and Multiplexers
 Examples of Multiplexers
• 2-to-1 Multiplexer
d0
Inputs Output
if (S == 0) Y = d0 ;
Y
S d0 d1 Y

2-to-1
Mux
d1
else Y = d1; 0 =
0 0 X
d0
Logic expression: 1 =
0 1 X

S
d0
0 =
1 X 0
Inputs d1 Output
• 4-to-1 Multiplexer
d0
1 =
S11 S0 X d0 1d1 d2 dd3 Y
if (S1S0 == 00) Y = d0 ;
d1
1
0 0 0 X X X 0 = d0
4-to-1 Y
d2
else if (S1S0 == 01) Y = d1; 0 0 1 X X X 1 = d0
Mux 0 1 X 0 X X 0 = d1

d3
else if (S1S0 == 10) Y = d2; 0 1 X 1 X X 1 = d1
else Y = d3;
2
1 0 X X 0 X 0 = d2

S1 S0
1 0 X X 1 X 1 = d2
1 1 X X X 0 0 = d3
• Logic expression: 1 1 X X X 1 1 = d3

ITCS 222– Computer Organization slide #19 Decoders, Encoders, and Multiplexers
 Implementing Multiplexers

d0
d0 2-to-1
Mux Y
d1
d1 Enabling
S AND Gates

S d0

d0
d1

d1
d2 Y
4-to-1

d2
Mux

d3
d3
2
Enabling

S1 S0
S1 AND Gates
S0

ITCS 222– Computer Organization slide #20 Decoders, Encoders, and Multiplexers
 Implementing Multiplexers (cont'd)
A Multiplexer can also be d0

implemented using:

4-to-
1 Mux
d1

1) A decoder and
Y
d2

2) Three-state gates 3-State

d3

(buffers)
Gates
2

d0
S1 S0

3-State d1
Gates
d0 Y
d2
d0
Y
2-to-
1 Mux

d1 d3
Y
d1

S 1-to-2
S1 2-to-4
Decod
er S0 Decod
er
S

ITCS 222– Computer Organization slide #21 Decoders, Encoders, and Multiplexers
 Building Larger Multiplexers
Larger multiplexers can be built hierarchically using smaller ones
Example #2: Building 8-to-1 MUX using
Example #1: Building 4-to-1 two 4-to-1 MUXes and a 2-to-1 MUX
MUX using three 2-to-1MUXes
d0 Question #2: What will be Y if
d0 d5

4-to-
1 Mux
d1 s2s1s0 = 101 ?
Mux

d1 d2
d0
d3
Mux

S0 Y d1
2

8-to-1 Mux
d2

Mux
S1 S0 Y d2
Mux

S1 d3
d3 Y
d4 d4
S0 S2
4-to-
1 Mux
d5 d5
Question #1: d6 d6
d7 d7
What will be Y if s1s0 = 11 ? 3
2
S2 S1 S0
d3 S1 S0
ITCS 222– Computer Organization slide #22 Decoders, Encoders, and Multiplexers
 Multiplexers with Vector Input and Output
Each input and each output of a MUX can be m-bit vectors
Generic 2-to-1 Multiplexer
Inputs and outputs are m-bit vectors
Generic 4-to-1 Multiplexer
Using m copies of a 2-to-1 MUX
Inputs and outputs are m-bit vectors
Using m copies of a 4-to-1 MUX

A [m–1:0]
2-to-1

m
Mux

Y [m–1: 0]
A [m–1:0]
m
B [m–1:0] m
B

4-to-
1 Mux
m [m–1:0]
m Y [m–1: 0]
C [m–1:0] m
m
S D [m–1:0]
m 2

S1 S0
ITCS 222– Computer Organization slide #23 Decoders, Encoders, and Multiplexers
 BCD to 7-Segment Decoder
• A seven-segment display is used to display one
decimal digit ( 0 to 9).
 Found in electronic devices: such as clocks, calculators, etc.
 Made of seven segments: light-emitting diodes (LED)

a
I3
 The display is controlled by a BCD to 7-segment decoder.
b
BCD to c
I2
7-Segment d
I1 e
I0 Decoder f
 A BCD to 7-Segment Decoder
 Accepts as input a BCD decimal digit (0 to 9) g
 Generates output to the seven LED segments to display the BCD digit
 Each segment can be turned on or off separately
ITCS 222– Computer Organization slide #24 Decoders, Encoders, and Multiplexers
 BCD to 7-Segment Decoder
Truth Table
Specification:
BCD input 7-Segment Output
 Input: 4-bit BCD (I3, I2, I1, I0) I3 I2 I1 I0 a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
 Output: 7-bit (a, b, c, d, e, f, g)
0 0 0 1 0 1 1 0 0 0 0
 Display should be OFF for Non-BCD
0 0 1 0 1 1 0 1 1 0 1
input codes.
0 0 1 1 1 1 1 1 0 0 1
Implementation uses: 0 1 0 0 0 1 1 0 0 1 1
 A binary decoder 0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
 Additional gates
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1010 to 0 0 0 0 0 0 0
1111
ITCS 222– Computer Organization slide #25 Decoders, Encoders, and Multiplexers
 Implementing a BCD to 7-Segment Decoder

a
Truth Table
I3 I2 I1 I0 a b c d e f

b
g
0
0 0 0 0 1 1 1 1 1 1

c
1 0
2
0 0 0 1 0 1 1 0 0 0

d
I3 4-to-10 3 0
I2 4 0 0 1 0 1 1 0 1 1 0

e
I1 Binary 5 1
I0 Decoder 6 0 0 1 1 1 1 1 1 0 0
7 1

f
8 0 1 0 0 0 1 1 0 0 1
1
9

g
0 1 0 1 1 0 1 1 0 1
𝑰 𝟑 (𝑰 𝟐 +𝑰 𝟏 ) 1

• NOR gate is used for 0's (a, b, c, d

0 1 1 0 1 0 1 1 1 1
Input > 9 1
• OR gate
0 is1used
1 1for 1e 1only
1 0 0 0
0
ITCS 222– Computer Organization slide #26 Decoders, Encoders, and Multiplexers
 Combinational Circuit Design
• A combinational circuit is a block of logic gates having:
inputs:

outputs:

• Each output is a function of the input variables

• Each output is determined from present combination of inputs
• A combinational circuit performs operation specified by its logic
gates

Combinational
inputs outputs



Circuit
ITCS 222– Computer Organization slide #27 Decoders, Encoders, and Multiplexers
 Combinational Circuit Example: Full Adder
• Design a Full adder to add 3 bits: a, b, and c Truth Table
• Two output bits: a a b c su cout
𝒔𝒖𝒎 m
1) Carry bit: cout b Full
0 0 0 0 0
2) Sum bit: sum
c
Adder 𝒄𝒐𝒖𝒕 0 0 1 1 0
0 1 0 1 0
• Sum bit is 1 if the number of 1's in the input
0 1 1 0 1
value is odd (odd function)
1 0 0 1 0
sum = (a  b)  c
1 0 1 0 1
• Carry bit is 1 if the number of 1's in the
1 1 0 0 1
input is 2 or 3
1 1 1 1 1
cout = a·b + (a  b)·c
ITCS 222– Computer Organization slide #28 Decoders, Encoders, and Multiplexers
 Combinational
Full AdderCircuit
Module Design
// Code in Verlog Language

module Full_Adder(input a, b, c, output cout,

sum); a b c
Full_Adder
wire w1, w2, w3;
w1
and (w1, a, b);

xor (w2, a, b);

w3 w2
and (w3, w2, c);

xor (sum, w2, c);

a
or (cout, w1, w3); 𝒔𝒖𝒎
Full
b
Endmodule c Adder 𝒄𝒐𝒖𝒕 cout sum
ITCS 222– Computer Organization slide #29 Decoders, Encoders, and Multiplexers
 Arithmetic and Logic Unit (ALU)
ALU Symbol
A [n - B [n -
• ALU performs many operations such as:
Arithmetic operations: ADD, SUB (Subtract) 1:0] 1:0]
n n

F
Logic operations: AND, OR, XOR, etc.

[2:0]
• Example: design an ALU with 8 operations 3
ALU

R [n -
as shown in the table below. VC n

1:0]
 The function of F is coded with 3 bits: F2 F1 F0.

Function ALU Result Function ALU Result

F = 100
F = 000 (ADD) R=A+B (AND) R=A&B
F = 001 (ADD +
1) R=A+B+1 F = 101 (OR) R=A|B
F = 110
F = 010 (SUB – 1) R=A–B–1 (XOR) R=A^B
F =Decoders,
111 Encoders, and
R =Multiplexers
~(A |
F=
ITCS 011
222– (SUB)
Computer R
Organization =A–B slide #30
(NOR) B)
 Designing a Simple ALU
R [n-1:0 = A[n-1:0] OP B[n-1:0]
A [n-1:0] B [n-1:0] F [2:0] = 3-bit Function code

n 𝐹1
n XOR n n n n n n
gates
n n n AND n OR n XOR
gates gates gates
cn-1 n
n-bit Adder c0 𝐹0 n ′
𝐹2𝐹 𝐹0
1 𝐹 2 𝐹 ❑1 𝐹 0 n
cn ′ ′ ❑ ′
𝐹2𝐹1𝐹0 𝐹2𝐹1 𝐹0
n
3-state ′
𝐹2
buffers n n n n
n Result Bus

V = Overflow 3-state buffers control the

VC C = Carry output R [n-1:0] output on the result bus
ITCS 222– Computer Organization slide #31 Decoders, Encoders, and Multiplexers
Combinational Circuit Design Steps (optional)
1) Specification
 Specify the inputs, outputs, and what the circuit should do

2) Formulation
 Convert the specification into truth tables or logic expressions for
outputs
3) Logic Minimization
 Minimize the output functions using K-map or Boolean algebra

4) Technology Mapping
 Draw a logic diagram using ANDs, ORs, and inverters
 Map the logic diagram into the selected technology
 Considerations: cost, delays, fan-in, fan-out

5) Verification
 Verify the correctness of the design, either manually or using simulation
ITCS 222– Computer Organization slide #32 Decoders, Encoders, and Multiplexers
 BCD to 7-Segment Decoder (optional)
• Seven-Segment Display is used to display decimal
digits 0 to 9.
 Made of Seven segments: light-emitting diodes (LED)
 Found in electronic devices: such as clocks, calculators, etc.
 The display is controlled by a BCD to 7-segment decoder.

a
I3 BCD to b
I2 c
7-Segment d
I1 e
I0 Decoder f
g
 A BCD to 7-Segment Decoder
 Accepts as input a BCD decimal digit (0 to 9)
 Generates output to the seven LED segments to display the BCD digit
 Each segment can be turned on or off separately
ITCS 222– Computer Organization slide #33 Decoders, Encoders, and Multiplexers
Designing a BCD to 7-Segment Decoder (optional)
1. Specification: Truth Table
 Input: 4-bit BCD (A, B, C, D)
BCD input 7-Segment decoder
 Output: 7-bit (a, b, c, d, e, f, g) A B C D a b c d e f g
 Display should be OFF for 0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
Non-BCD input codes
0 0 1 0 1 1 0 1 1 0 1
2. Formulation 0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
 Done with a truth table
0 1 0 1 1 0 1 1 0 1 1
 Output is zero for 1010 to 0 1 1 0 1 0 1 1 1 1 1
1111 0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1010 to 0 0 0 0 0 0 0
1111
ITCS 222– Computer Organization slide #34 Decoders, Encoders, and Multiplexers
Designing a BCD to 7-Segment Decoder (optional)
3. Logic Minimization Using K-Maps
𝐶𝐷 K-map for 𝐶𝐷 K-map for 𝐶𝐷 K-map for
𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10
00 1 1 1 00 1 1 1 1 00 1 1 1
01 1 1 1 01 1 1 01 1 1 1 1
11 11 11
10 1 1 10 1 1 10 1 1

Optimized Logic Expressions

Extracting common terms

Let are shared gates

ITCS 222– Computer Organization slide #35 Decoders, Encoders, and Multiplexers
Designing a BCD to 7-Segment Decoder (optional)

3. Logic Minimization Using K-Maps

𝐶𝐷 K-map for 𝐶𝐷 K-map for 𝐶𝐷 K-map for 𝐶𝐷 K-map for
𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10
00 1 1 1 00 1 1 00 1 00 1 1
01 1 1 01 1 01 1 1 1 01 1 1 1
11 11 11 11

10 1 1 10 1 10 1 1 10 1 1

Common AND Terms Optimized Logic Expressions

 Shared Gates

ITCS 222– Computer Organization slide #36 Decoders, Encoders, and Multiplexers
Designing a BCD to 7-Segment Decoder (optional)
4. Technology Mapping A T4
B'
T2
Many Common AND terms: thru C'
D' T5
B' T6
A'
C T0
D' T7
Optimized Logic Expressions
C' T8
A'
T1
B
D' T9

Showing only
Outputs e, f, g e f g
ITCS 222– Computer Organization slide #37 Decoders, Encoders, and Multiplexers
 Example of Hierarchical Design (optional)
• Top Level: 16-input odd function: 16 inputs, one output
• Second Level: Five 4-input odd functions
• Third Level: Three 2-input XOR gates
x0
x0 x0 x0 x1
x1 x1 x1 4-Input z
x2 x2 x2 Odd z x2
x3 x3 x3 Function x3
x4 x4 x0
x5 x1 4-Input
x5
x6 x2 Odd z
16-Input x6 x0
x7 x3 Function x1 4-Input
z x7 x0 Odd z z
x8 Odd x8 x2
4-Input
x9 x9 x1 x3 Function
x2 Odd z
x10 Function x10
x3 Function Hierarchical Design
x11 x11
x12 x12 x0 typically includes
x1 4-Input
x13
x13
x2 Odd z blocks of different
x14 x14
x15 x3 Function functions and size
x15

ITCS 222– Computer Organization slide #38 Decoders, Encoders, and Multiplexers
Top-Down versus Bottom-Up Design (optional)

• A top-down design proceeds from a high-level

specification to a more and more detailed design by
decomposition and successive refinement

• A bottom-up design starts with detailed primitive

blocks and combines them into larger and more
complex functional blocks

• Design usually proceeds top-down to a known set of

building blocks, ranging from complete processors to
primitive logic gates
ITCS 222– Computer Organization slide #39 Decoders, Encoders, and Multiplexers
 Testing Hierarchical Design (optional)
• Exhaustive testing can be very time consuming (or impossible)
 For a 16-bit input, there are 216 = 65,536 test cases (combinations)

 For a 32-bit input, there are 232 = 4,294,967,296 test cases

 For a 64-bit input, there are 264 = 18,446,744,073,709,551,616

test cases!

• Testing a hierarchical design requires a different strategy

• Test each block in the hierarchy separately
 For smaller blocks, exhaustive testing can be done

 It is easier to detect errors in smaller blocks before testing complete circuit

• Test the top-level design by applying selected test inputs

• Make sure that the test inputs exercise all parts of the circuit
ITCS 222– Computer Organization slide #40 Decoders, Encoders, and Multiplexers
 Iterative Design (optional)
• Using identical copies of a smaller circuit to build a large circuit
• Example: Building a 4-bit adder using 4 copies of a full-adder
• The cell (iterative block) is a full adder
Adds 3 bits: ai, bi, ci, Computes: Sum si and Carry-out ci+1
• Carry-out of cell i becomes carry-in to cell (i +1)
a3 b3 a2 b2 a1 b1 a0 b0 ai bi

c4 Full c3 Full c2 Full c1 Full c0 ci+1 Full ci

Adder Adder Adder Adder Adder

s3 s2 s1 s0 si

ITCS 222– Computer Organization slide #41 Decoders, Encoders, and Multiplexers
 Hierarchical Design in Verilog (optional)
// Module Odd_4: 4-input Odd function uses three xor gates
module Odd_4 (input [0:3] x, output z);
wire [0:1] w;
xor g1(w[0], x[0], x[1]);
xor g2(w[1], x[2], x[3]);
xor g3(z, w[0], w[1]);
endmodule

// Module Odd_16: 16-input Odd function

module Odd_16 (input [0:15] x, output z);
wire [0:3] w;
Odd_4 block0 (x[0:3], w[0]);
Odd_4 block1 (x[4:7], w[1]);
Five instances of
Odd_4 block2 (x[8:11], w[2]);
Odd_4 block3 (x[12:15], w[3]); the Odd_4 module
Odd_4 block4 (w[0:3], z);
endmodule

ITCS 222– Computer Organization slide #42 Decoders, Encoders, and Multiplexers
 Bit Vectors in Verilog (optional)
• A Bit Vector is multi-bit declaration that uses a single name
• A Bit Vector is specified as a Range [msb:lsb]
• msb is most-significant bit and lsb is least-significant bit
• Examples:
input [0:15] x; // x is a 16-bit input vector

wire [0:3] w; // Bit 0 is most-significant bit

reg [7:0] a; // Bit 7 is most-significant bit

• Bit select: w[1] is bit 1 of vector w

• Part select: x[8:11] is a 4-bit select of x with range [8:11]
• The part select range must be consistent with vector
declaration
ITCS 222– Computer Organization slide #43 Decoders, Encoders, and Multiplexers
 16-Bit Adder Module (optional)
// Input ports: 16-bit a and b, 1-bit cin (carry input)
// Output ports: 16-bit sum, 1-bit cout (carry output)
module Adder_16 (input [15:0] a, b, input cin,
output [15:0] sum, output cout);
wire [16:0] c; // carry bits
assign c[0] = cin; // carry input
assign cout = c[16]; // carry output
// Instantiate an array of 16 Full Adders
// Each instance [i] is connected to bit select [i]
Full_Adder adder [15:0] (a[15:0], b[15:0], c[15:0],
c[16:1], sum[15:0]);
endmodule

Array Instantiation of identical modules by a single statement

ITCS 222– Computer Organization slide #44 Decoders, Encoders, and Multiplexers
 Testing the 16-bit Adder (optional)
• Exhaustive testing: 216 × 216 × 2 = 8,589,934,592 test cases
• Let us choose only: 3 × 3 × 2 = 18 test cases
• Input test cases for a[15:0] = 'h158A, 'h52AF, 'hB903
Chosen randomly with values shown in hexadecimal
'h158A (hexadecimal) = 'b0001_0101_1000_1010 (binary)
Underscores are ignored (used to enhance readability)
• Input test cases for b[15:0] = 'h7095, 'h9A4E, 'hC6BD
Also chosen randomly with values shown in hexadecimal
Radix symbol: 'b (binary), 'o (octal), 'd (decimal), 'h (hex)
• Input test cases for cin = 0, 1
ITCS 222– Computer Organization slide #45 Decoders, Encoders, and Multiplexers
Writing a Test bench for the 16-bit Adder (optional)
module Test_Adder_16; // Test bench for Adder_16
reg [15:0] A, B; reg Cin; // Data and Carry inputs
wire [15:0] Sum; wire Cout; // Sum and Carry outputs
Adder_16 Test (A, B, Cin, Sum, Cout); // Instantiate 16-bit
adder
initial begin
A='h158A; B='h7095; Cin=0; // Initialize A, B, Cin
#200 $finish; // At t=200 end simulation
end
always begin // Change A every 60 ns
#60 A='h52AF; #60 A='hB903; #60 A='h158A;
end
always begin // Change B every 20 ns
#20 B='h9A4E; #20 B='hC6BD; #20 B='h7095;
end
always #10 Cin = ~Cin; // Invert Cin every 10 ns
endmodule
ITCS 222– Computer Organization slide #46 Decoders, Encoders, and Multiplexers
 Simulator Waveforms (optional)

• The values of A, B, and Sum are shown in hexadecimal

Can change the radix to binary, octal, and decimal
• The values of Sum and Cout can be verified easily
• All 18 test cases of A, B, and Cin are generated (t=0 to 180 ns)
ITCS 222– Computer Organization slide #47 Decoders, Encoders, and Multiplexers