Chapter Three

Boolean Algebra
 Laws and Rules of Boolean Algebra
Laws of Boolean Algebra

The basic laws of Boolean Algebra

 the Commutative law of addition for two variables is written as
A+B = B+A , This law applied to the OR gate

the Commutative law of Multiplication

AB = BA , This law applied to the AND gate
 Cont’d
 Associative law of addition is written as follows for three
variables. A+(B+C) = (A+B)+C ,
This law applied to more than two input OR gate

Associative law of multiplication is written as follows for three variables.

A.(B.C) = (A.B).C
 Cont’d
Distributive Law the distributive law is written for three variables as
follows. A(B+C) = AB+AC
 Cont’d
 Identity Law
0 is an Identity element of Addition Operation A+0=A
1 is an Identity element of Multiplication Operation A.1 = A
 Complement Law
Complement Law of Addition A +AC=1
Complement Law of Multiplication A.AC=0
Other Laws Boolean Algebra
6. A .0 = 0 10. A.(A + B) = A
7. A .A = A 11. (A + B).(A+C) = A + B.C
8. A’’ = A 12. A + Ā.B =A + B
9. A + A.B =A ‘proof it’ 13. A.(Ā +B) = A.B
14. (A + B).(Ā + C) = A.C + Ā.B
15. (A + C).(Ā + B) = A.B + Ā.C
 Cont’d

 Demorgan’s Theorems
I Theorem statement:
The complement of a sum is equal to the product of the
complements.
___ _ _
A+B=A.B

II Theorem Statement:
The complement of a product is equal to the sum of the
complements.
____ _ _
A.B=A+B
 Standard Forms of Boolean Expressions
 All Boolean expressions can be converted in to either of two standard
forms: the sum-of-products (SOP) form or the product-of-sums
(POS)form.

The Sum–of–Products (SOP) form

When two or more product terms are summed by Boolean addition the

result expressed by SOP.

 A SOP expression can be implemented by AND-OR logic gate
Implementing simply requires ORing the output of two or more AND
gates.
Eg. AB+ABC
ABC+CDE+B’CD’
Domain of a Boolean Expression the domain of general Boolean
 expression is the set of variables contained in the expression in either
 complemented or uncomplemented form. Eg. ABC’+CD’E+B’CD’
 Cont’d
Eg.
 X = AB + BCD + AC
(Using AND gates)

or

 X = AB + BCD + AC
(Using NAND gates)

 Covert the following expression to SOP form

AB + B(CD + EF)
A(B + C) + BC(A + C)
 Converting SOP Expressions to truth table format

 Converting a truth table to an expression

1. Each row with output of 1 becomes a product term
2. Sum the product terms together.

x y z G
0 0 0 0 • For SOP representation, select rows with 1’s
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

xyz + xyz’ + x’yz

 Cont’d
Number of 1’s in truth table output column equals AND terms for Sum-of-
Products (SOP)

x y z G
0 0 0 0
0 0 1 0
0 1 0 0 x x
0 1 1 1 x
G
1 0 0 0 x
x
1 0 1 0 x
1 1 0 1 x
1 1 1 1 x
x

x y z
G = xyz + xyz’ + x’yz
 The Product–of–Sum (POS) form
 When two or more sum terms are producted by Boolean mulitplication
the result expressed by POS.
 a POS expression can be implemented by OR-AND logic gate
Implementing simply requires ANDing the output of two or more OR
gates.
 To implement the truth table of POS ckt consider the output of the
binary values equal to zero. Eg. (A+B).(C+D).(A+B+C)
(A+B+C).(C+D+E).(B’+C+D’)
Domain of a Boolean Expression the domain of general Boolean
 expression is the set of variables contained in the expression in either
 complemented or un complemented form. (A+B+C).(C+D+E).(B’+C+D’)

 X=(A+B).(B+C+D).(A+C)
Converting POS Expressions to truth table format
 Converting a truth table to an expression
1. Each row with output of 0 becomes a Sum term
2. Product Sum terms together.

x y z G
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

(A+B+C).(A+B+C’).(A+B’+C).(A’+B+C).(A’+B+C’)

• For POS representation, select rows with 0’s

 Converting Standard SOP to standard POS

 To convert from standard SOP to standard POS

 Evaluate each product term in the SOP expression. Determine
the binary numbers that represent the product terms
 Determine all of the binary numbers not included in the
evaluation in step 1.
 Write the equivalent sum term for each binary numbers from
Step 2 and express in POS forms.

Convert the following SOP expression to an equivalent POS expression:

Soln:- the evaluation is as follow

000+010+011+101+111
 Cont’d
 Since there are three variables in the domain of this expression, there
are
a total of eight possible combinations. The SOP expression contains five
of these combinations, so the POS must contain the other three which
are
001, 100, and 110.

 Remember, these are the binary values that make the sum term 0. The
equivalent POS expression is
 Minterms
Minterms(standard product) a binary variable may appear either in its
normal form(x) or in its complement form(x’).Now consider two binary
variables x and y combined with an AND operation. Since each variable
may appear in either form, there are four possible combinations: x’y’, x’y,
xy’, and xy. Each of these four AND terms representation is called
minterm (standard product).
 The convenient way of expressing using the sum symbol ∑
 N variables can be combined to form 2n minterms.
The binary numbers from 0 to 2n - 1 are listed under the n
variables.
Each minterms variable being primed if the corresponding bit of
the binary number is 0 and unprimed if it is 1.
Minterm is symbolized by mj ,where j denotes the decimal
equivalent of the binary number of the miniterm.
 Cont’d
 Each AND combination of terms is a minterm

For example:
Minterms

x y z Minterm
0 0 0 x’y’z’ m0
0 0 1 x’y’z m1
…
1 0 0 xy’z’ m4
…
1 1 1 xyz m7
 Cont’d
• Minterm representation, select rows with 1’s
• Minterm number same as row position in truth table
• Shorthand way to represent functions ∑
x y z G
0 0 0 0
0 0 1 0 G = xyz + xyz’ + x’yz
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0 G = m7 + m6 + m3 = Σ(3, 6, 7)
1 1 0 1
1 1 1 1
 Maxterms
Maxterms (standard sum) A binary variable may appear either in its
normal form(x) or in its complement form(x’).Now consider two binary
variables x and y combined with an OR operation. Since each variable
may appear in either form, there are four possible combinations: x’+y’,
x’+ y, x+y’, and x+y. Each of these four OR terms representation is
called maxterms (standard sum).
 The convenient way of expressing using the product symbol
N variables can be combined to form 2n maxterms.
The binary numbers from 0 to 2n - 1 are listed under the n
variables.
Each maxterms variable being unprimed if the corresponding bit of
the binary number is 0 and primed if it is 1.
Maxterms is symbolized by Mj ,where j denotes the decimal
equivalent of the binary number of the maxterm.
Note that each maxterms is the complement of its corresponding
minterm, and vice versal
Cont’d
 Cont’d
 A Boolean function can be expressed algebraically from a given truth
table by forming a minerms for each combination of variables that
produces a 1 in the function.

Example
a) f1 = x’y’z + xy’z’ + xyz = m1 + m4 + m7
b) f2 = x’yz + xy’z + xyz’ + xyz = m3 + m5 + m6 + m7
 Cont’d
 A Boolean function can be expressed algebraically from a given truth
table by forming a maxterms for each combination of variables that
produces a 0 in the function.
using the above truth table form a Boolean function
 f1’ (minterms) = f1(maxterm)
f1(maxterms) = (x+y+z)(x+y’+z)(x+y’+z’)(x’+y+z’)(x’+y+z)
= M0*M2*M3*M5*M6
f2’ (minterms) = f2(maxterm)
f2(maxterms) = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
= M0*M1*M2*M4
 Boolean functions expressed as a sum of minterms or product of
maxterms
are said to be in Canonical form.
 Cont’d
• Easy to convert between minterm(SOP) and maxterm(POS)
representations
• For maxterm representation, select rows with 1’s
x y z G
0 0 0 0 G = xyz + xyz’ + x’yz
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0 G = m7 + m6 + m3 = Σ(3, 6, 7)
1 0 1 0
1 1 0 1
1 1 1 1
G = M0M1M2M4M5 = Π(0,1,2,4,5)

G = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)(x’+y+z’)
 Sum of minterms

 It was previously stated that for n binary variables, one can obtain 2n
 distinct minterms, and that any Boolean function can be expressed as
a
 sum of minterms.
 The minterms whose sum defines the Boolean function are those that
 give the 1’s of the function in a truth table.

Example
 a) Expess the Boolean funcction F = A + B’C in a sum of minterms.

Exercise
 Product of maxterms
 It was previously stated that for n binary variables, one can obtain 2n
 distinct maxterms, and that any Boolean function can be expressed as
a
 product of maxterms.
 The maxterms whose product defines the Boolean function are those
 that give the 0’s of the function in a truth table.
Example
 a) Expess the Boolean funcction F = xy + x’z in a product of
 maxterms.
Soln: first convert the function in to OR terms using the distribution law:
Cont’d
Simplification of Boolean Function using Karnaugh Map method
 A Karnaugh map provides a systematic method for simplifying Boolean
 expressions and, if properly used, will produce the simplest SOP or POS
 expression possible, known as the minimum expression.
 The map method, first proposed by Veitch and modified by Karnaugh, is
 also known as the “Veitch diagram” or the “Karnaugh map.”
 The Kmap is a diagram made up of squares. Each square represents one
 minterms.
karnaugh map for two variable
 There are four minterms for two variables; hence, the map consists of four

square, one for each minterm. Notice that A prime appears in row 0 and
unprimed in row 1. Similarly, B prime appears in column 0 and unprimed
in column 1.
 The possible values of the variable A are written down the left hand side
of
the map, labelling the corresponding row of the map, while the possible
values of the variable B are written along the top of the map, labelling the
corresponding columns of the map.
 Cont’d

m0 m1
m2 m3

The map show the relation between the squares and the two variables
 Note that the minterms are arranged in binary sequence, but in
sequence
similar to the Gray code
Example:- F= x’y + xy’ + xy = m1 + m2 + m3
Mark the three square with 1’s. these squares found from the minterms of
the function
the simplification of F is
F=x+y
 karnaugh map for three variable
 There are eight minterms for three variables; hence, the map consists
of
eight square, one for each minterm. Notice that A prime appears in row
0
and unprimed in row 1. Similarly, B prime appears in column 0,1 and
unprimed in column 2,3.
 The possible values of the variable A are written down the left hand
side
of the map, labelling the corresponding row of the map, while the
possible values of the variable B and C are written along the top of the
map, labelling the corresponding columns of the map.
 Cont’d
Example
1.Simplify the Boolean function using Kmap
a) F(A, B, C) = ∑ (2, 3, 4, 5)
b) F(A, B, C) = ∑ (3, 4, 6, 7)
c) F(A, B, C) = ∑ (0,2, 4, 5, 6)
2. Given the following Boolean function:
F = A’C + A’B + AB’C + BC
a) Express it in sum of miniterms.
b) Find the simplified sum of products(SOP) expression

Exercise
1.Simplify the Boolean function using Kmap
a) A’B + BC’ + B’C’
b) AB + A’B’C’ + A’BC’
c) A’B’ + BC + A’BC”
 karnaugh map for four variable
 There are Sixteen minterms for four variables; hence, the map consists
of
sixteen square, one for each minterm. Notice that A prime appears in
row
0,1 and unprimed in row 2,3. and B prime appears in row 0,3 and
unprimed in column 1,2. similarly C prime appeared in column 0,1 and
unprimed in column 2,3 and D prime appeared in column 0,3 and
unprimed appear 1,2.
 The possible values of the variable A and B are written down the left
hand side of the map, labelling the corresponding row of the map,
while
the possible values of the variable C and D are written along the top of
the
m0 map,
m1 labelling
m3 m2 the corresponding columns of the map.
m4 m5 m7 m6
m12 m13 m15 m14
m8 m9 m11 m10
 karnaugh map for five variable
 In the case of 5-variables, it is convenient to use two 16-cell maps
rather than one 32-cell map, as shown in Figure below. The right-hand
map is allocated to the true(A=1) value of A, while the left-hand map is
associated with the complement (A=0) of variable A.
 The possible values of the variable A, B and C are written down the left
hand side of the map, labelling the corresponding row of the map,
while
the possible values of the variable D and E are written along the top of
the map, labelling the corresponding columns of the map.
 The minterms 0 through 15 belong with A = 0 and minterms 16 through
31 with A = 1
 Cont’d

Example
1.Simplify the Boolean function Kmap method
a) F(A, B, C, D, E) = ∑ (0, 2, 8, 10, 21, 23, 29, 31)

Exercise
1.Simplify the Boolean function Kmap method
a) F(A, B, C, D, E) = ∑ (0,2,3,4,5,6,7,8,11,15,16,18,19,23,27,31)
b) F(v, w, x, y, z) = ∑ (0,1,4,5,16,17,21,25,29)
c) F = A’B’C’D’E’+A’B’C’DE’+A’B’CD’E’+A’B’CDE’+
A’BC’D’E’+A’BC’DE’+ A’BCD’E’+A’BCDE’+
AB’C’D’E’+ABC’DE’+AB’C’DE’+ABC’D’E’+ABC’DE’
 “Don’t Care” Condition
 Sometimes a situation arises in which some input variable
combination are not allowed. For example there are six invalid
BCD combinations: 1010,1011,1100,1101,1110, and 1111. since
these invalid state will never occur in an application involving the
BCD code. They can be treated as “don’t care” terms with
respect to their effect on the output.
 For these “don’t care” terms either a 1 or 0 may be assigned to
the output; it really does not matter since they will never occur.
 The “don’t care’’ terms can be used to advantage on the
karnaugh map simplification method.
Example:- mark X in the don’t care terms, if the don’t care terms
used to simplification change X by 1s and we get the simpler
result,if not the don’t care condition does not matter for
simplification.
a) Simplify the Boolean function F(w,x,y,z) = ∑(7,8,9)
that has the don’t care condition d(w,x,y,z) = ∑(10,11,12,13,14,15)
 Cont’d

 Chapter Four

Combinational Logic Analysis

Introduction
 Introduction
 A combinational circuit consists of logic gates whose
outputs at any time are determined directly from the present
combination of inputs without considering to previous inputs.

 A combinational circuit consists of input variables, logic gates,

and output variables.

 The n input binary variables comes from an external source; the

m output variables go to an external destination. The block
diagram shows a combinational circuit.
 Cont’d
 For n input variables, there are 2n possible combinations of
binary
output values. For each possible input combination, there is one
and only one possible output combinational. Each output
function is expressed in terms of the n input variables.
 Each input variable to a combinational circuit may have one or
two wires. When only one wire is available, it represent the
variable either in the normal form (un-primed) or in complement
form(primed).
 Design Procedure of Combinational Circuit
The design of combinational circuits starts from the verbal outline
of the problem and set Boolean functions, ends in logic circuit
diagram . The procedure involves the following steps:
1. The problem stated
2. The number of available input variables and required output
variables is determined.
 Cont’d

3. The input and output variables are assigned letter symbols.

4. Draw the truth table that defines the required relationships
between inputs and outputs variable.
5. The simplified Boolean function for each output is obtained.
6. Draw logic diagram.

When you Design a combinational circuit you must be check the

following point:-
a. Minimum number of gates
b. Minimum number of inputs to a gate
c. Minimum propagation time of the signal through the circuit
d. Minimum number of interconnections
 Arithmetic Circuit (Adders and Subtractors)
 Digital computer perform the arithmetic operations addition is
called adders.
 A combinational circuit performs the addition of two Single bit
binary number is called a half adder.
 This circuit needs two binary inputs and two binary output S
(sum) and C (carry) to the outputs.
Half Adders
A0 B0 C1 S0 A0
S0
0 0 0 0
B0
0 1 0 1
1 0 0 1 C1
1 1 1 0
 The carry output is 0 unless both inputs are 1. The S output
represents the least significant bit of the sum.
 Cont’d
 The simplified Boolean functions for the two outputs can be
obtained directly from the truth table.
The simplified sum of products expressions are
S0 = A’B + AB’ and C1 = AB

Block Diagram
Representation of Half Adder

Different logic diagram representation of Half Adder


Cont’d
 Full Adder
A full adder is a combinational circuit that forms the arithmetic
 sum of three input bits. It consists of three inputs and two
 outputs.
The three input variables denoted by x ,y and z. The
 two output denoted by S (sum) and C(carry). As shown below
X Y Z C S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1

0 1 1 1 0

1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 Cont’d
Implementation of Full Adder using AND-OR Gate Network

Block diagram representation of

Implementation of Full Adder
Full Adder
using XOR Gate Network
A B

Cin Full Cout

adder

Sum
Implementation of Full Adder using Two Half Adders
 A full adder can be made from two half adders (plus an OR
gate).
S=XY’Z’ +X’YZ’ + XYZ + X’Y’Z C= XY’Z + X’YZ + XYZ’+XYZ
= Z’ (XY’+X’Y) + Z (XY + X’Y’) = XY’Z + X’YZ + XY(Z’+Z)
= Z’ (XY’ + X’Y) + Z (XY’ + X’Y)’ = XY’Z + X’YZ + XY
= Z(XY’ + X’Y) + XY
=Z (X Y) = Z(X Y) + XY

X S

Z
C
 Parallel Binary Subtractor
 Parallel subtractor is a digital circuit that produces the arithmetic
subtraction of two binary numbers.
 To construct a parallel binary subtractors connect/cascade the
output borrow of each full subtractor to the input borrow of the next
higher-order full subtractor. As shown in the fig below
.

 An n-bit subtractor requires n-full subtractors with each borrow output

connected to the input borrow of the next full subtractors.

 Overflow
In order to obtain a correct answer when adding and subtracting,
we must ensure that the result has a sufficient number of bits to
accommodate the sum.

If we start with two n-bit numbers and we end up with a number
that is n+1 bits, we say an overflow has occurred.
 Decoder and Encoder
Decoder  information
A decoder is a combinational circuit that converts binary
from n input lines to a maximum of 2 unique output lines
n

 The process of converting from coded format to familiar symbols or

numbers is called Decoding.
 Any combinational circuit with n input can be implemented with
an n-to-2n line decoder .
 A decoder is a minterm generator

 Can be developed using AND/OR gates

 Example, consider the 2-to-4 line decoder circuit. The two inputs
are decoded into four outputs, each output representing one of the
minterms of the 2-input variables. The two inverters provide the
complement of the inputs, and each one of the four AND gates
generates provides one of the minterms.
 2-to-4 line Decoder
Block diagram representation
2-to-4 line decoder
Output

Truth Table

Binary number i/p

 3-to-8 line Decoder
As an example, consider the 3-to-8 line decoder circuit. The
three inputs are decoded into eight outputs, each output
representing one of the minterms of the 3-input variables.
The three inverters provide the complement of the inputs,
and each one of the eight AND gates generates provides one
of the minterms.
Block diagram representation 3-to-8 line decoder
 Cont’d
 A 3-to-8 (binary-to-octal number s/m)line Decoder

Truth Table Octal number o/p

Binary number i/p

 Decoder with Enable Input
A decoder can have an additional input signal called the enable which
enables or disables the output generated by the decoder.

2-to-4 line Decoder with Enable input

 Cont’d
3-to-8 line Decoder with Enable input

A A A D D D D D D D D
E
2 1 0 0 1 2 3 4 5 6 7
3
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
 Encoders
 An encoder is a digital circuit that performs the inverse operation
of a decoder. An encoder has 2n input lines and n output lines.
 Can be developed using OR gates

Block diagram representation 2n-to-n line encoder

 A encoder is a maxterm generator

The process of converting from familiar symbols or numbers to a coded
format is called Encoding.
 Example, consider the 4-to-2 line encoder circuit. The four inputs
are encoded into 2 outputs, each output representing one of the
maxterms of the 4-input variables.
 4-to-2 line Encoder
Block diagram representation
 line encoder
4-to-2
Truth Table
Input output

 Draw the logic circuit diagram of 4-to-2 line encoder

 8-to-3 line Encoder
 Example, consider the 8-to-3 line encoder circuit. The 8 inputs
are encoded into 3 outputs, each output representing one of the
maxterms of the 8-input variables.

Block diagram representation

23-to-3 line encoder
 Cont’d
Inputs
Outputs
 Priority Encoder
A priority encoder is an encoder circuit that includes the priority
function, The operation of the priority encoder is such that if two or
more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.

 From the above truth table, you observe that only one input can
be active at any given time. If two inputs are active simultaneously, the
output produces an undefined combination.

Example, if D3 and D7 are 1 simultaneously, the output of the encoder

will be 111 because all three outputs are equal to 1.This does not
represent binary 3 nor binary 7.
To resolve this ambiguity , encoder circuits must establish a priority to
ensure that only one input is encoded. If we establish a higher priority
for inputs with higher subscript numbers, and if both D3 and D6 are 1
at the same time, the output will be 110 because D6 has higher priority
than D3.
 Multiplexers and Demultipexers
Multiplexers A multiplexer(MUX) is a combinational circuit that selects
(Data Selectors) binary information from one of may input lines and directs it
to a single output line.
A multiplexer have 2n input lines and n selection lines whose
bit combinations determine which input is selected and 1
output line. Block diagram representation of
2 -to-1 line Multiplexer
n

Multiplexer means transmitting

a large number of information

over a smaller number of
channels or lines.

Multiplexer also is known as data selector.

A multiplexer is often abbreviated as MUX.
 cont’d
Example ,a 4-to-1 line multiplexer ,Each of the four input lines, D0

to D3, is applied
Block to one input of an AND gate. Selection lines S1
diagram
and S0 are decoded to select a particular AND gate.

Truth Table
 Cont’d
A multiplexer is also called a data selector, since it selects one of
the many inputs and steers the binary information to the output
line.

In general 2n-to-1 line multiplexer is constructed from an

n-to-2n decoder by adding to it 2n input lines, one to each AND gate.

The size of multiplexer is specified by the number 2n of its input

lines and the single output line. It is then implied that it also
contains n selection lines.
 Demultipexers (Data Distributers)
A demultiplexer(DEMUX) basically reverses the multiplexing
function. It takes digital information from one line and distributes
it to a given number of output lines.
The demultiplexer is also known as a data distributor.
 A encoder can also be used as demultiplexer.
 1-line-to-4-line Demultiplexer

Block diagram
1*4 DMUX

Logic diagram
Truth Table
S1 S0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
 1 line to 8 line demultiplexers

A 1 line to 8 line
demultiplexer.