SV –Data Structure and

Control flow
-Geethanjali G
Agenda

 Data Structures

 Arrays

 Packed Arrays

 Unpacked Arrays

 Array Slicing

 Dynamic Arrays

 Associative Arrays

 Queues

 System Verilog Control flows

Types of Data Structures
 Array : is collection of same data type,which can be accessed with name and an
index.
ex: bit [7:0] arr_y [1:256]; // [7:0] is the vector width, [1:256] is the array size
Types of array :
 Packed and Unpacked arrays
 Dynamic arrays
 Associative arrays

 Queues
Packed Arrays
Packed array

 A packed array is a mechanism for subdividing a vector into subfields which can be
conveniently accessed as array elements.
 Packed arrays refer to the dimension declared before the object name.
 Ex : bit [3:0] b;

 Ex : logic [3:0] [7:0] a; //a 32-bit vector with 4 “8-bit subfieds”

Limitation of packed array: Only bit, logic, reg can be used in packed array.
Variables with predefined length cannot be used as packed array like byte, integer, longint,
shortint, int.
Un-packed Arrays

Un-Packed array

 Unpacked arrays refer to the dimensions declared after the object name
 Unpacked arrays can be made of any type
 Only access a single element at a time

ex: bit a [3:0];

ex : bit [7:0] b_unpack[3] or bit [7:0] b_unpacked [2:0] both same;

pack_unpack_array.sv
Multi-dimensional Arrays
Arrays of instances can be multidimensional. Example:
Array Slicing
Array Slicing:

Allows selection and assignment of one or more contiguous elements of an array.

In other words Selecting a part from an array is slicing

Ex:
logic [63:0] data;
array_slicing.sv
logic [7:0] byte1;
byte1 [3:0] = data [32:35];
byte2 [7:4] = data [48:51];

Array Indexing :
logic [6:0] [7:0] a;
logic [:0] b;
b = a[0]; // It assigns 8 bits of a[0] to b
Dynamic Arrays
 It is an unpacked array, whose size can be set or changed at run-time.
 Dynamic declaration of one-dimensional arrays.

Syntax: data type array_name[]; Ex : int data[]; array_methods_new_size_dele_op.sv

 The example declares a dynamic array to store integers.

 The number of integers in the array is not known at the time of declaration and
no space is created yet.
 The memory space needs to be explicitly created during run-time.
 In built Operators on Dynamic Arrays
 new [ ] – Sets or changes the size of the array
 size ( ) – Returns the current size of the array
 delete ( ) – Clears all elements of the array, to a zero-size empty array
Dynamic Arrays :ex

dynamic_arr.sv
Associative Arrays

 The associative array is an indexed array, where the element is linked with an index
variable.
 index can be wildcard(any integral value), string, integer, class, packed array, unpacked
array.
 Associative arrays do not have any storage allocated until it is used. The size of the array is
unknown.

Examples:

int array_name[*]; //Wildcard index ,can be indexed by any integral data type.
int array_name [string] ; // String index
int array_name [some class]; // Class index
int array_name [integer]; // Integer index
Ex : Associative Arrays - sparse memory model
Associative Array Methods

 Num ( )
 Return the number of entries in the associative array
 Delete ( )
 Removes the entry at the specified index
 Exists ( )
 Checks if an element exists at the specified index
 Returns 1 if it exists; else returns 0
 First ( )
 Assigns the index variable passed, with the first index in the associative array
 Returns 0 if the array is empty; else returns 1
 Last ( ) associative_ar.sv
 Assigns the index variable passed, with the last index in the associative array
 Returns 0 if the array is empty; else returns 1
 Next ( )
 Assigns the index variable passed, with the next index in the associative array
 Returns 0 if next element does not exist; else returns 1
 Previous ( )
 Assigns the index variable passed, with the previous index in the associative
array
 Returns 0 if next element does not exist; else returns 1
Queues
 Variable size array with automatic sizing, It is a single dimension (un-packed array).

 Each element in the queue is identified by a number which represents its position
 Supports searching, sorting, and insertion methods.
 0 represents the first position
 $ represents the last position
 It can grow and shrink automatically
 Declaration :
 e.g.(1) integer int_q [ $ ] ; // Un-initialized queue of integers
 e.g.(2) string str_q [$:100] ; // Queue of strings with maximum of 100 entries
Queue Methods

 Size ( )
 Returns the number of elements in the queue.

 Insert ( )
 Inserts the specified element to the specified index location.

 Delete ( )
 Deletes an element at the specified index location
Queue Methods

 Pop_front ( )
 Removes and returns the first element of the queue.
 e.g. ele = Q.pop_front( ); is same as ele = Q[0] ; Q = Q[1:$] ;

 Pop_back ( )
 Removes and returns the last element of the queue.
 e.g. ele = Q.pop_back( ); is same as ele = Q[$] ; Q = Q[1:$-1] ;

 Push_front ( )
 Inserts a given element as the first element in the queue
 e.g. Q.push_front(ele) ; is same as Q = {ele, Q} ;

 Push_back ( )
 Inserts a given element to the end of the queue
 e.g. Q.push_back(ele) ; is same as Q = {Q, ele} ;
Structures and Unions
Structure is a collection of objects that can be of different data types

• Can be used to bundle several variables into one object.

• Can pass structures through ports and to tasks or functions.

• Data members can be referenced individually (using the . operator) or altogether as a unit.

• Structure can be packed or unpacked.

• structure allocates the memory equal to the total memory required by the members.

• structure enables us treat a number of different variables stored at different in memory.

• each member have their own memory space.

Structures and Unions

struct {
int a //Members of structure
byte b;
bit [7:0] c
} struct_data;

Struct_data.c = 8’h1E;
Structures and Unions cont..
Structure can be defined using “typedef”

typedef struct { Structure can be Initialized :

bit [7:0] opcode;

bit [23:0] addr;
} instruction; // named structure type

instruction IR; // define variable

IR a[9:0]; // array of structures

Unpacked vs Packed Structures
Packed : A packed structure consists of bit fields, which are packed together in memory
without gaps.

Ex: you might pack together the opcode and operand fields to make a value that contains
an entire processor instruction.

Limitation : Only integer types (bit, logic, int, reg, time) can be used in a packed structure.

unpacked : An unpacked structure has an implementation-dependent packing.

Each member can be assigned differently.
Unpacked vs Packed Structures cont..
Structure can be packed signed/unsigned

structure.sv

If any data type within a packed structure is 4-state, the whole structure is treated as 4-
state. Any 2-state members are converted ( cast ).
Unions
• A union allows us to treat the same space in memory as a number of different
variables.

• All members begin at the same memory address , ie one block is used by all the
member of the union.

union {
int a;
byte b;
bit [7:0] c;
} my_data;

• Memory allocation for the above defined union "my_data".

System Verilog – Control flows

• Control flows are constructs that controls the flow of a process in a program
.

Types of Control Flow :

1. Selection
2. Loops
3. Jumps
4. Tasks and Functions
Selection statement
If and case statements are the selection statements.

Enhancements in Selection Statements in SV:

1. Unique if
2. Priority if
3. Unique case
4. Priority case
unique if

Features:
Syntax: unique if(condition)
<statement>
else if(condition)
1. Each line is mutually exclusive and unique. <statement>
else
2. A unique if indicates that there should not be any <statement>

overlap in a series of if...else...if conditions.

3. Issues warning when there is no condition match
unless there is a explicit else and if more than 1 unique_if.sv

statement is true.
priority if , unique case priority case

Features:

1. The order of evaluation is important.

2. When 1 condition is true the following ones are not evaluated.

3. A priority if indicates that a series of if...else...if conditions shall be evaluated in

the order listed.

4. Issues warning when there is no condition match unless there is an explicit else.

priority_case.sv unique_case.sv priority_if.sv

Loops

Loops : A set of statements are executed many times.

Types of loops:
 forever
 repeat
 while

Enhancements in SystemVerilog
 do….while
 foreach
 enhanced for loop
forever

forever : This loop continues until the simulation is interrupted by $finish.

Syntax: forever <statement>
Ex:
forever.sv
repeat

The repeat loop executes statement a fixed number of times.

syntax : repeat (< number >) < statement >
Example :
repeat.sv
Enhanced for loop

1. Ability to declare the for loop control variable within the for loop.
2. Same variables can be declared in different procedural blocks.
3. ++ operator can be used which is not there in verilog.

syntax : for (< initial assignment >; < expression >, < step assignment >)
< statement >

Example :
forloop.sv
while and do…while

Syntax: while (condition)

<statement>
Syntax: do
<statement> while_do_while.sv

while (condition)
foreach
The maximum value of the index in the foreach loop is decided by the size of the declared array

Syntax: foreach(array name[index variable])

module foreach_loop ();

byte a [10] = {0,6,7,4,5,66,77,99,22,11};

initial
begin
foreach (a[i])
begin
$display (“The array contents are %d",a[i]);
end
#1 $finish;
end

endmodule
Jump break and continue

Jumps: Program execution stepping from one place to another.

SystemVerilog adds the C jump statements break, continue and return.

break : Control comes out of loop as C

continue : skip to end of loop as C break.sv continue.sv

return expression : exit from a function

return : exit from a task or void function
return expression
This returns a value. It is used only in functions and not in tasks.

Syntax: return <expression>

//return statement which does not return any value://

Syntax : return
return.sv

Does not return any value. Just used to come out of the void function or
task.
Tasks and Functions

 Gives the ability to execute common procedures from several

different places. Same functionality called at many places in the TB.

 Input ,output, inout argument values can be passed into a task and
only input arguments into functions.
Tasks

 Declared with the Keywords “task” and “endtask”

 When to use tasks ?
Delay, timing or event control constructs present in
procedure
Procedure has 0 or more than 1 output arguments
Procedure has 0 or more input arguments
Task-Basic concepts

 Must be defined in a module ,class .

 Can have input, output and inout arguments.
 Can also have local variables, registers, time variables, integers or events.
 Contain behavioral statements only.
 Do not contain always or initial statements but are called from these blocks,
or other tasks and functions.
 Input and output arguments are passed into the task.
 Input arguments are processed in the task statements.
 Output and inout argument values are passed back to variables in task
invocation statement.
 Task exits when endtask is reached – Verilog.
 return statement can be used to exit task before endtask keyword – System
Verilog.
Tasks

Task Syntax:

task < task_name>;

//port declarations//
begin task_intro.sv

<statements>

end

endtask
Functions

 Declared with the Keywords “function” and “endfunction”

 When to use functions ?
No Delay, timing or event control constructs in the procedure
Procedure returns a single value
Atleast 1 input argument
No output or inout arguments
No non-blocking assignments
Functions-Basic concepts
 Must be defined in a module ,class and is local to it

 Can have only input arguments

 No output and inout arguments

 Can also have local variables, registers, time variables, integers or events

 Provides exactly one output

 Do not contain always or initial statements but are called from these blocks,
or other tasks and functions

 Can invoke only other functions and NOT OTHER TASKS

Function arguments

 System verilog extends Verilog functions to allow same formal arguments

 Function argument directions :
 input
 output
 inout
 ref

 Default formal direction – input

 Default function argument type - logic
Functions :ex

 Example :
function logic [15:0] example(int a, int b, output logic [15:0] u, v);
…….
endfunction

 a, b : default to inputs
 u, v : Both are outputs
 begin…..end can be omitted – Sequential execution is maintained
Function - Example
module function_intro ();
bit a ;

initial begin
#1 a = doInit(4,5);
#1 a = doInit(9,6);
#1 $finish;
end

function bit unsigned doInit (bit [3:0] count, add);

reg [7:0] b;
if (count > 5) begin
$display ("@%g Returning from function", $time); function_intro.sv
return 0;
end
b = add;
$display ("@%g Value passed is %d", $time, count
+ b);
doInit = 1;
endfunction

endmodule
Void function

System Verilog allows using void data type to discard a function’s return value(no
return value)
module function_discard ();
bit a ;
Eg. : void ‘(function_name()); initial begin
#1 void'(doInit(4,5));
#1 void'(doInit(9,6));
#1 $finish;
end
function bit unsigned doInit (bit [3:0] count, add);
reg [7:0] b;
if (count > 5) begin
$display ("@%g Returning from function", $time);

end
b = add;
$display ("@%g Value passed is %d", $time, count + b);

endfunction
endmodule
Argument passing in function /task

Two means of passing arguments

Pass by Value Pass by reference

Pass by value

 Default mechanism for passing arguments to subroutines(method -> task or function)

 Copies each argument to subroutine area

 Subroutine retain a local copy of arguments in its stack.

 Changes within subroutine – not visible outside

fun_pass_by_value.sv

task pass_v (int unsigned x, int unsigned y = 10);

endtask
Pass by reference

 Arguments are passed by reference

 Argument must be matched with equivalent data types

 Reference to original argument is passed – ref keyword

 The task/function can then access the argument data via the reference.
 Both the caller and the subroutine share the same representation of the
argument

function void pack(const ref bytes[]);

endfunction
Pass by reference - ex

function_pass_by_ref.sv
Tasks and Function

Attributes Tasks Functions

Default port Input Input

direction
Default Data Logic Logic
Type
Begin….End No need to use No need to use

Return Can be used Can be used

Wire Cannot be used Cannot be used

in portlist in portlist
Task/Function Differences

Functions Tasks

Cannot contain time Can contain time

controlling statements
Function cannot enable A task can enable other
a task tasks and functions
Function should have Tasks can have zero or
atleast 1 argument more arguments
Function cannot contain Can contain input ,inout
output or inout and output
Function returns a single Tasks does not return
value or no value. any value.
 Process execution threads
 fork...join

Statements that follow a “fork...join” are blocked from execution until all the processes have completed

execution.

 fork...join_any

Statements that follow a “fork...join_any” are blocked from execution until any one of the processes has

completed execution.

 fork...join_none

Statements that follow a “fork...join_none “are not blocked from execution while the processes are executing.

Does not wait for any forked process is complete and thus starts execution statements after the join_none

statement without waiting for forked process.

Process execution threads cont..
fork
fork
execute();
execute();
begin
begin
generate();
generate();
check();
check();
end
end
join_none
join_none

fork_join.sv fork_join_any.sv fork_join_none.sv

In the example code :

The execute() task runs in parallel with the begin-end block.
The tasks generate() and check() run serially