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Lecture 27

The document discusses the programmed I/O driver for handling input from 32 character input devices, detailing the structure of data and control registers, polling mechanisms, and the role of interrupts. It explains the differences between vectored and non-vectored interrupts, the functioning of interrupt service routines, and the importance of switching between user mode and supervisor mode during system calls. Additionally, it covers the interrupt vector table and its significance in managing interrupts in 8086/8088 architecture.

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2 views

Lecture 27

The document discusses the programmed I/O driver for handling input from 32 character input devices, detailing the structure of data and control registers, polling mechanisms, and the role of interrupts. It explains the differences between vectored and non-vectored interrupts, the functioning of interrupt service routines, and the importance of switching between user mode and supervisor mode during system calls. Additionally, it covers the interrupt vector table and its significance in managing interrupts in 8086/8088 architecture.

Uploaded by

imaan maqsood
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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CS501

Advanced Computer
Architecture
Lecture 27

Dr.Noor Muhammad Sheikh


Review
Programmed I/O Driver
for 32 character Input
Devices
Assumptions
• Device driver can handle input from 32
different character input devices, at once.
• Each input device has its own data and
control registers.
• The control register has a Ready status bit
in position 31
• The data register can only be read and
returns the character in bits 7..0.
Continued
• The data and control register’s address begins
at address FFFFF300H.
• Thus the 32 devices occupy word address
from FFFF300H to FFFFF3FCH.
• The device driver will input and store a line of
characters from each device.
• Each line determinated by a carriage return.
• The driver is capable of handling input from all
32 devices by polling.
Continued

“Polling is a process by which the device


driver tests each device in some
predetermine order of priority, to see if it
has a character ready.”
Continued
• Input from each device is controlled by 2
words
• The first contain a pointer into a buffer.
• The second is Done flag.
• If Done flag is 0 then the device is actively
receiving characters.
• If Done flag is -1, the device will be
inactive.
Fig. 8.10 (jordan)
Interrupt Driven I/O
Program Flow
Program Flow

Key Board Serial Port Key Board


Interrupt Interrupt Interrupt
Types of Interrupts
Interrupt Service routine
Continued
• Software interrupts are usually associated
with the software.
• A simple output operation in a multitasking
system requires software interrupts to be
generated.
• Output is usually handled by interrupts so
that it appears interactive and asynchronous.
• Notification of other events, such as expiry of
a software timer is also handled by software
interrupts.
• Software interrupts are also used with system
calls.
• When the operating system switches from
user mod e to supervisor mode it does so
through software interrupts.
• Consider an example where a user program
must delete a file.
• The user program will be executing in the user
mode
• When it makes the specific system call to
delete the file, a software interrupt will be
generated.
• This will cause the processor to halt its
current activity and switch to supervisor
mode.
• Once in supervisor mode, the operating
system will delete the file and then control
will return to the user program.
• In supervisor mode the operating system
would decide if it could delete the specified
file with out harmful.
• It is important that the system switch to
super visor mode at each system call.
• It is a routine which is executed when an
interrupt occurs.

• Also known as Interrupt Service Routine


(ISR)

• Deals with low-level events in the


hardware of a computer system like a tick
of a real-time clock.
• An interrupt once generated must be
serviced through an interrupt service
routine.

• These routines are stored in the system


memory ready for execution.

• Once the interrupt is generated, the


processor must branch to the location of
the appropriate service routine to execute
it.
Vectored and Non Vectored
Interrupts
• The branch address of the interrupt
service routine is fixed.

• The code for the ISR is loaded at fixed


memory location.

• Very easy to implement and not flexible at


all.
• The number of peripheral devices is fixed
and may not be increased.

• Once the interrupt is generated the


processor queries each device.

• The processor does this to find out which


device generated the interrup.
Vectored Interrupt
Vector Interrupt
• Used to specify the address of the
interrupt service routine.
• The ode for ISR can be loaded anywhere
in the memory.
• This approach is much more flexible.
• Using vectored interrupts, multiple devices
may share the same interrupt input line.
• A process called daisy chaining is then
used to locate the interrupting device.
Interrupt vector is a fixed size structure that
stores the address of the first instruction of
the ISR.
• All of the interrupt vectors are stored in the
memory in this table.

• Interrupt Vector Table is loaded at the


memory location 0 for the 8086/8088.
• Interrupts in 8086/8088 are vector
interrupts.
• Interrupt vector is of 4 bytes to store IP
and CS.
• Interrupt vector table is loaded at address
0 of main memory.
• There is provision of 256 interrupts.
• The number of interrupt is the number of
interrupt vector in the interrupt vector
table.
• Since size of each vector is 4 bytes.
• Interrupt vector starts from address 0.
• The address of interrupt vector can be
calculated by simply multiplying the
number by 4.
Interrupt Handling
Interrupt Latency
Summary
User Level I\O Software

Device-Independent Operating System


Software
Device Drivers

Interrupts Handlers

hardware
In 8086/8080 machines Code Segment
a +3
the size of interrupt (Most Significant Byte)
vector is 4bytes that
holds IP and CS of Code Segment
a +2
ISR. (Least Significant Byte)
Instruction Pointer
a +1
(Most significant Byte)
Instruction Pointer
a
(Least Significant Byte)

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