Unit-V

Registers and Counters: Introduction, Registers, Shift

Registers, Ripple Counters: Up counter, Up-Down
counter, Synchronous Counters: Up Counter, Up-
Down counter, Decade Counter, Other Counters: Ring
Counter, Johnson Counter
 Introduction
Registers and Counters:
 Counters are mainly used in counting applications, where they
either measure the time interval between two unknown time
instants or measure the frequency of a given signal, registers are
primarily used for the temporary storage of data present at the
output of a digital circuit before they are fed to another digital
circuit.
 Flip-flop is a 1 bit memory cell which can be used for storing the
digital data.
 To increase the storage capacity in terms of number of bits, we have
to use a group of flip-flop. Such a group of flip-flop is known as
a Register.
 The n-bit register will consist of n number of flip-flop and it is
capable of storing an n-bit word.
 The binary data in a register can be moved within the register from
one flip-flop to another. The registers that allow such data transfers
are called as shift registers.
Shift Register:
A group of flip flops which is used to store multiple bits of data and the data is
moved from one flip flop to another is known as Shift Register.

The bits stored in registers shifted when the clock pulse is applied
within and inside or outside the registers.
To form an n-bit shift register, we have to connect n number of flip
flops. So, the number of bits of the binary number is directly proportional to the
number of flip flops.

The flip flops are connected in such a way that the first flip flop's output
becomes the input of the other flip flop.

A Shift Register can shift the bits either to the left or to the right. A Shift
Register, which shifts the bit to the left, is known as "Shift left register", and it
shifts the bit to the right, known as "Right left register".
 Types of Shift Registers
 There are four mode of operations of a shift register.
• Serial Input Serial Output
• Serial Input Parallel Output
• Parallel Input Serial Output
• Parallel Input Parallel Output
1) Serial Input Serial Output
Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0.
If an entry of a four bit binary number 1 1 1 1 is made into the register, this
number should be applied to Din bit with the LSB bit applied first. The D
input of FF-3 i.e. D3 is connected to serial data input Din. Output of FF-3 i.e.
Q3 is connected to the input of the next flip-flop i.e. D2 and so on.
Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of
the number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first
falling edge of clock, the FF-3 is set, and stored word in the register is
Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits,
FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q 3 Q2 Q1 Q0 =
1110.
Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored
word in the register is Q3 Q2 Q1 Q0 = 1111.
2) Serial Input Parallel Output:
• In such types of operations, the data is entered serially and
taken out in parallel fashion.
• Data is loaded bit by bit.The outputs are disabled as long as
the data is loading.
• As soon as the data loading gets completed, all the flip-
flops contain their required data, the outputs are enabled
so that all the loaded data is made available over all the
output lines at the same time.
3) Parallel Input Serial Output (PISO):
• Data bits are entered in parallel fashion.
• The circuit shown below is a four bit parallel input serial output register.
• Output of previous Flip Flop is connected to the input of the next one via a combinational
circuit.
• The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
There are two modes in which this circuit can work namely - shift mode or load mode.
Load mode
 When the shift/load bar line is low (0), the AND gate 2, 4 and 6
become active they will pass B1, B2, B3 bits to the corresponding
flip-flops.
 On the low going edge of clock, the binary input B 0, B1, B2, B3 will
get loaded into the corresponding flip-flops.
 Thus parallel loading takes place.

Shift mode
 When the shift/load bar line is low (1), the AND gate 2, 4 and 6
become inactive. Hence the parallel loading of the data becomes
impossible.
 But the AND gate 1,3 and 5 become active. Therefore the shifting
of data from left to right bit by bit on application of clock pulses.
 Thus the parallel in serial out operation takes place.
4) Parallel Input Parallel Output (PIPO):
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data
inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a
negative clock edge is applied, the input binary bits will be loaded into
the flip-flops simultaneously. The loaded bits will appear simultaneously
to the output side. Only clock pulse is essential to load all the bits.
 Counters
 A special type of sequential circuit used to count the pulse is known
as a counter, or a collection of flip flops where the clock signal is
applied is known as counters.
 The counter is one of the widest applications of the flip flop. Based
on the clock pulse, the output of the counter contains a predefined
state.
 The number of the pulse can be counted using the output of the
counter.
 Counters are broadly divided into two categories

• Asynchronous counter (Ripple Counter)

• Synchronous counter
1. Asynchronous Counter:
These are the counters in which we do not use universal clock, main clock is only
applied to the first flip flop and then for rest of flip flops the output of previous
flip flop is taken as a clock.

Asynchronous counter using JK-Flip flop

Asynchronous counter using T-Flip flop

2. Synchronous Counter:
These are the counters in which we use a universal clock that is common to all
flip flops. The Circuit diagram of Synchronous Counter is given Below:
 Difference between Synchronous and Asynchronous Counter
S.NO Synchronous Counter Asynchronous Counter
In asynchronous counter main clock is only
In synchronous counter we use a universal
applied to the first flip flop and then for rest of
1. clock that is common to all flip flops
flip flops the output of previous flip flop is
through out the circuit.
taken as a clock.
Synchronous Counter is faster in operation Asynchronous Counter is slower as compared
2.
as compared to Asynchronous Counter. to synchronous counter in operation.
Synchronous Counter does not produce Asynchronous Counter produces decoding
3.
any decoding errors. error.
Synchronous Counter is also called Parallel Asynchronous Counter is also called Serial
4.
Counter. Counter.
Synchronous Counter designing as well
Asynchronous Counter designing as well as
5. implementation are complex due to
implementation is very easy.
increasing the number of states.
Synchronous Counter will operate in any Asynchronous Counter will operate only in
6.
desired count sequence. fixed count sequence (UP/DOWN).
Synchronous Counter examples are: Asynchronous Counter examples are: Ripple UP
7.
Ring counter, Johnson counter. counter, Ripple DOWN counter.
In synchronous counter, propagation delay In asynchronous counter, there is high
8.
is less. propagation delay.
 Other Counters
Up Counter : 0,1,2,3,4,5,6,7,8,9,………
Down Counter : 9,8,7,6,5,4,3,2,1,0,------
Up Down Counter : 0-9 and 9-0
Mod-N or Modulus-N Counter
The number of different output states a counter can produce is called the
modulo or modulus of the counter. The Modulus (or MOD-number) of a
counter is the total number of unique states it passes through in one complete
counting cycle with a mod-n counter being described also as a divide-by-n
counter. Or The number of states or stages
Ex: Mod-8 counter N= Mod-8 counter or 3-bit counter
8=
=
n=3 Therefore 3 Flip-flops required
Q1: Design 2 bit Asynchronous/Ripple UP counter or Design Mod-4 Asynchronous
counter using JK Flip-Flop
• Identify number of flip-flops required for designing Mod-4 or 2 bit Asynchronous counter.
• MOD-N Represent the number of stages or states means 00,01,10,11 are four stages
• Each flip flop is capable of storing only one bit information ( 0 or 1)
• Changing the binary number from 0-1 or 1-0 is toggle. In JK flip flop toggle operation
will be done when clk=1, j=1 and k=1

Clock Counter State Up

Output number Counte
r
Output

Initially 0 0 - 0
1st 0 1 1 1
2nd 1 0 2 2
3rd 1 1 3 3
4th 0 0 4 0
 3 bit Asynchronous down counter /Mod-8 using JK
Flip-Flop
• Identify number of flip-flops required for designing Mod-8 or 3 bit Asynchronous
counter.
• MOD-8 or the 3 bit counter, we require 3 flip flops and we can generate 2 3 = 8 state and
count (111 110 … 000).
• Each flip flop is capable of storing only one bit information ( 0 or 1)
• Changing the binary number from 0-1 or 1-0 is toggle. In JK flip flop toggle operation
will be done when clk=1, j=1 and k=1
Clock Counter State Down
Output num Counte
ber r
Output

Initiall 0 0 0 - 0
y
1st 1 1 1 1 7
2nd 1 1 0 2 6
3rd 1 0 1 3 5
4th 1 0 0 4 4
5th 0 1 1 5 3
6th 0 1 0 6 2
7th 0 0 1 7 1
8th 0 0 0 8 0
Design of 3 bit Asynchronous up/down counter :
 It is used more than separate up or down counter.
 In this a mode control input (say M) is used for selecting up and down
mode.
 A combinational circuit is required between each pair of flip-flop to
decide whether to do up or do down counting.
Steps involve in design are :
Step 1 : Decision for Mode control input –
Decision for mode control input
When M = 0, then Y= Q, therefore it will perform Up counting
When M = 1, then Y= Q’ therefore it will perform Down counting.
Combinational circuit is required for deciding mode control(i.e whether counter will
perform Up counting or Down counting).
So the all possible combinations are –

K-map for finding output Y that will

be given as clock to next FF.
Step 2 : Insertion of Combinational logic between every pair of FFs –
Case 1 – When M=0, then M’ =1.
Put this in Y= M’Q + MQ’= Q So Q is acting as clock for next FFs.
Therefore, the counter will act as Up counter.
Explanation of Up counter –
The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
The 2nd FF input is connected to Q1.Therefore it changes its state when Q1= 1 and there is
falling edge of clock.
Similarly, 3rd FF is connected to Q2. Therefore, it changes its state when Q2= 1 and there is
falling edge of clock.
By this we can generate counting states of Up counter.
After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
Case 2 – When M=1, then M’ =0.
Put this in Y= M’Q + MQ’= Q’. So Q’ is acting as clock for next FFs.
Therefore, the counter will act as Down counter.
Explanation of Down counter –
The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
The 2nd FF input is connected to Q’1.Therefore it changes its state when Q’1= 1 and there is
falling edge of clock.
Similarly, 3rd FF is connected to Q’2. Therefore, it changes its state when Q’2= 1 and there is
falling edge of clock.
By this we can generate counting states of down counter.
After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
 Asynchronous Decade Counter
 Modulo-16 asynchronous counter and modified it with additional logic gates it can be
made to give a decade (divide-by-10) counter output for use in standard decimal
counting and arithmetic circuits. Such counters are generally referred to as Decade
Counters.
 A decade counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this
condition back to the reset input.
 A counter with a count sequence from binary “0000” (BCD = “0”) through to “1001”
(BCD = “9”) is generally referred to as a BCD binary-coded-decimal counter because
its ten state sequence is that of a BCD code but binary decade counters are more
common.
 Output bit Pattern
Clock Decimal
Count Value
QD QC QB QA

1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 Counter Resets its Outputs back to Zero
 Synchronous Counters
How to Design Synchronous Counters
Step 1: Decide the number of flip-flops.
Step 2: Excitation Table of required flip-flop.
Step 3: Sate diagram and Characteristic table
Step 4: Use K-Maps to obtain simplified equations.
Step 5: Draw the Logic diagram.
Mod-4 Synchronous Up Counter using JK flip-Flop
Step 1: Decide the number of flip-flops.
Here we are performing 2 bit or mod-4 Up counting, so 2- Flip Flops are required,
which can count up to 22-1 =3 . Here JK Flip Flop is used.
Step 2: Excitation Table of required flip-flop.

Qt Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Step 3: Sate diagram and Characteristic table
Step 4: Use K-Maps to obtain simplified equations.

Step 5: Draw the Logic diagram.

 Design of 4-bit Synchronous Up-Counter
Step 1: Decide the number of flip-flops.
• The number of flip-flops required are decided by the number of bits required by the
counter.
•In this case we will need four flip-flops as the maximum number “15" is "1111" in
binary which needs 4-bits.
For this purpose we will use JK flip-flops (You may also use D or T flip-flops).
Step 2: Excitation Table of required flip-flop.
Since we chose JK flip-flop, let us write the excitation table for JK flip-flop

Qt Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Step 3: State Diagram and Characteristic table.
Step 4: Find a simplified equation using k map –
Step 5: Create a circuit diagram –
 Synchronous Down Counter
Design 3 bit Synchronous Down Counter using T flip-flop
Step 1: Decide the number of flip-flops.
Here we are performing 2 bit or mod-4 Down counting, so 3- Flip Flops are
required, which can count up to 23-1 =7 . Here T Flip Flop is used.
Step 2: Excitation Table of required flip-flop.
Qt Qt+1 T
0 0 0
0 1 1
1 0 0
1 1 1

Step 3: Draw State diagram and circuit excitation table –

Characteristic table:

Qt Qt+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Step 4: k-map representation
 Synchronous 3 bit Up/Down counter
Steps to design Synchronous 3 bit Up/Down Counter :
1. Decide the number and type of FF –
 Here we are performing 3 bit or mod-8 Up or Down counting, so 3 Flip Flops are
required, which can count up to 23-1 = 7. Here T Flip Flop is used.
2. Write excitation table of Flip Flop –

3. Decision for Mode control input M –

 When M=0 ,then the counter will perform up counting.
 When M=1 ,then the counter will perform down counting.
4. Draw the state transition diagram and circuit excitation table –
5. Circuit excitation table –
6. Find a simplified equation using k map –
Here we are finding the minimal Boolean expression for each Flip Flop input T using k
map.
7. Create a circuit diagram –

8. Timing Diagram –
After every falling edge, when T = 1, the output state of Flip Flop will toggle.
Initially Q3 = 0 , Q2= 0 , Q1= 0.
Case 1 : When M=0 ,then M’= 1
T3 = M’Q2Q1 + MQ’2Q’1 = Q2Q1.
T2 = M’Q1 + MQ’1= 1.Q1= Q1.
T1= 1.
Because T1= 1, therefore FF1 output state toggles for every falling edge.
The output state of FF 2 will toggle when Q1 = 1 and the falling edge of the clock pulse
occurs.
The output state of FF 3 will toggle only when Q2.Q1= 1 and the falling edge of the clock
pulse occurs.
In this way, after every falling edge, state transition takes place and we can get our desired
counting sequence.
Case 2 : When M=1 ,then M’ =0
T3 = M’Q2Q1+MQ’2Q’1 = Q’2Q’1
T2 = M’Q1+ MQ’1= 1.Q1= Q’1.
T1= 1.
Because T1= 1,therefore FF1 output state toggles for every falling edge.
The output state of FF 2 will toggle when Q’1 = 1 and the falling edge of the clock pulse
occurs.
The output state of FF 3 will toggle only when Q’2.Q’1= 1 and the falling edge of the clock
pulse occurs.
 Binary 4-bit Synchronous Decade Counter
Designing a 0 to 9 Synchronous Counter
Step 1: Decide the number of flip-flops.
• The number of flip-flops required are decided by the number of bits required by
the counter.
•In this case we will need four flip-flops as the maximum number "9" is "1001" in
binary which needs 4-bits.
For this purpose we will use JK flip-flops (You may also use D or T flip-flops).
Step 2: Excitation Table of required flip-flop.
Since we chose JK flip-flop, let us write the excitation table for JK flip-flop

Qt Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
 Step 2: State Diagram and Characteristic table.

Qt Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Characteristic table from excitation table of JK-Flip-Flop

Q1: Design MOD 5 Synchronous Counter using JK Flip-flop

Note: Mod-5 means 5 states (000,001,010,011,100) can be implemented by using 3-bit

number

Step 1: Find the number of Flip-flops needed

5 States/stages/posiblity can be accomplished by 3 bit value(a,b,c) for storing 3 bit

information into flip-flop we required 3 flip flops so number of flip flops required is 3

Step2: Write the excitation table of the flip-flop

Excitation table of JK flip-flop is

QN QN+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
3: Write the circuit state table by using excitation table
Circuit state table for designing MOD 5 Synchronous Counter using JK Flip-flop
would be Q Q J K
N N+1

Table---2( derived from table 1) 0 0 0 X

0 1 1 X
1 0 X 1
1 1 X 0
Shift Register:
shift register counters: Shift Register Counters are the shift
registers in which the outputs are connected back to the
inputs in order to produce particular sequences. These are
basically of two types:

1.Ring Counter
2.Johnson counter/Twisted Ring /Switch rail counter
 Shift Register Counters:
1.Ring Counter
A ring counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the output of the last flip flop is again fed
back to the input of the first flip flop, thus the name ring counter. The data pattern within
the shift register will circulate as long as clock pulses are applied.

Circuit Diagram of Ring counter Operation

2. Johnson counter
A Johnson counter is basically a shift register counter in which the output of the first
flip flop is connected to the next flip flop and so on and the inverted output of the last
flip flop is again fed back to the input of the first flip flop. They are also known as
twisted ring counters.

Operation Circuit Diagram of Ring counter

Applications of shift Registers –

 The shift registers are used for temporary data

storage.
 The shift registers are also used for data transfer and
data manipulation.
 The serial-in serial-out and parallel-in parallel-out
shift registers are used to produce time delay to
digital circuits.
 The serial-in parallel-out shift register is used to
convert serial data into parallel data thus they are
used in communication lines where demultiplexing
of a data line into several parallel line is required.
 A Parallel in Serial out shift register us used to
convert parallel data to serial data.