Unit-III

Introduction, Design Procedure, Combinational

circuit for Half Adder, Full Adder, Half Subtractor,
Full Subtractor, Binary Adder, Binary Adder-
Subtractor, Decimal Adder, Code Converters,
Decoders, Encoders, Multiplexers, Demultiplexers
 Combinational Circuit
• The combinational logic circuits are the circuits that contain different types
of logic gates.
• Simply, a circuit in which different types of logic gates are combined is
known as a combinational logic circuit.
• The output of the combinational circuit is determined from the present
combination of inputs, regardless of the previous input gates, and output
variables are the basic components of the combinational logic circuit.
• There are different types of combinational logic circuits, such as Adder,
Subtractor, Decoder, Encoder, Multiplexer, and De-multiplexer.
 Applications of Combinational Circuit
• NAND and NOR Implementation
• Digital Measuring Techniques
• Digital Processing
• Industrial Processing
• Computers
• Calculators
• Automatic control of machines
• Digital Communication.
 Design Procedure
• Step-1: Identify the number of inputs and
outputs of the circuit.
• Step-2: Creating the Truth Table.
• Step-3: Simplify the Boolean function for each
output.
• Step-4: Constructing circuit using Boolean
function obtained from third step.
 Half Adder
The Half-Adder is a basic building block of adding two numbers as two inputs
and produce out two outputs. The adder is used to perform OR operation of
two single bit binary numbers. The augent and addent bits are two input
states, and 'carry' and 'sum 'are two output states of the half adder.

Block diagram Truth Table

The SOP form of the sum and carry are as follows:

Sum = A‘B+AB'
Carry = AB
Logic Diagram for half Adder
Half Adder is also designed by combining the 'XOR' and 'AND' gates
and provide the sum and carry.

There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B
Carry= A AND B
 K-maps using for Half Adder
• The SOP form of the sum and carry are as follows:
• Sum = A‘B+AB'
Carry = AB
Implementation of Half Adder using NAND gates : Total 5 NAND gates are
required to implement half adder

A . 𝐴𝐵

𝐴𝐵

B. 𝐴𝐵
𝐴𝐵

Sum (S)=A+ B= A+ B+
= A+)+ B+)=A. + B. =

Carry (C)=AB=
Implementation of Half Adder using NOR gates : Total 5 NOR gates are required to
implement half adder.

Sum (S)=A+ B= A+ B+
= A+)+ B+)= +B)(+)
=

Carry (C)=AB= =
Limitation of Half Adder-

• Half adders have no scope of adding the carry bit

resulting from the addition of previous bits.
• This is a major drawback of half adders.
• This is because real time scenarios involve adding the
multiple number of bits which can not be accomplished
using half adders.
 Full Adder
• The half adder is used to add only two numbers. To overcome this problem,
the full adder was developed. The full adder is used to add three 1-bit binary
numbers A, B, and carry C. The full adder has three input states and two
output states i.e., sum and carry.

Truth Table
Block diagram

Sum = A' B' C+A' BC'+AB' C'+ABC

Carry = A’BCin+ AB’Cin+ABCin’+ABCin=AB(Cin+Cin’)+Cin(A’B+AB’)
=AB+Cin(A’B+AB’)
Construction of Full Adder Circuit:
 Realization of full Adder using two Half Adders and an OR gate Circuit:

The full adder logic circuit can be constructed using the 'AND' and the ‘XOR’ gate with an OR
gate.
 K-maps using for Full Adder
Sum = x' y' z+x' yz+xy' z'+xyz
Carry=X’YCin+XY’Cin+XYCin’+XYCin

The SOP form can be obtained with the help of K-map as:
Sum = x' y' z+x' yz+xy' z'+xyz
Carry = xy+xz+yz
Implementation of Full Adder using NAND gates:

A ⊕ B=
Where S= A ⊕ B ⊕=

= (A ⊕ B )+AB=
Implementation of Full Adder using NOR gates:

A ⊕ B=
Where S= A ⊕ B ⊕
=
= (A ⊕ B )+AB==
 Half Subtractor
Half subtractor is a combination circuit with two inputs and two outputs that
are different and borrow. It produces the difference between the two binary bits at the
input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In the
subtraction (A-B), A is called a Minuend bit and B is called a Subtrahend bit.

Block diagram Truth Table

The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB‘
Borrow = A'B
Implementation of Logic Diagram for Half Subtractor

Advantages of Half Adder and Half Subtractor

• Simplicity
• Building blocks
• Low cost
• Easy integration
Disadvantages of Half Adder and Half Subtractor
• Limited functionality
• Inefficient for multi-bit numbers
• High propagation delay
Application of Half Subtractor in Digital Logic:
1.Calculators
2.Alarm Frameworks
3.Automotive Frameworks
4.Security Frameworks
5.Computer Frameworks
Implementation of Half Subtractor using NAND gates :
Implementation of Half Subtractor using NOR gates :
 Full Subtractor
Loaded: 5.50%
Â

A full-subtractor is a combinational circuit that has three inputs A, B, bin and two
outputs d and b. Where, A is the minuend, B is subtrahend, b in is borrow produced by
the previous stage, d is the difference output and b is the borrow output.

Truth Table
Block diagram

Difference,d=A⊕B⊕bin=A′B′bin+AB′b′in+A′Bb′in+Abbin

Borrow,b=A′B′bin+A′Bb′in+A′Bbin+ABbin
Or
Borrow,b=A′B(bin+b′in)+(AB+A′B′)bin=A′B+(A⊕B)′bin
K-maps using for Full Subtractor

Diff=xy' z'+x' y' z+xyz+x'yz'

Borrow=x' z+x' y+yz

Realization of full Subtractor using two Half Subtractors and an OR gate Circuit:

The full subtractor logic circuit can be constructed using the 'AND', '
XOR', and NOT gate with an OR gate.
Implementation of Full Subtractor using NAND gates:

Implementation of Full Subtractor using NOR gates:

 Binary Adder
The Binary Adder is formed with the help of the Full-Adder circuit. The Full-Adders are
connected in series, and the output carry of the first Adder will be treated as the input
carry of the next Full-Adder.
N-Bit Parallel Adder
The Full Adder is used to sum two single-bit binary numbers with carry input. In digital
calculation, we need to add two n-bit binary numbers rather than only single-bit binary
numbers. For this purpose, we need to use n-bit parallel Adder. In order to get N-bit
parallel adder, we cascade the n number of Full Adders. The carry output of the first Adder
is treated as the carry input of the second Adder.
• The 'A' and 'B' are the augend, and addend bits are defined by the
subscript numbers. The subscripts start from right to left, and the lower-
order bit is defined by subscript '0'.
• The C0, C1, C2, and C3 are the carry inputs which are connected together
as a chain using Full Adder. The C4 is the carry output produced by the last
Full-Adder.
• The Cout of the first Adder is connected as the Cin of the next Full-Adder.
• The S0, S1, S2, and S3 are the sum outputs that produce the sum of
augend and addend bits.
• The inputs for the input variable 'A' and 'B' are fetched from different
source registers. For example, the bit for the input variable 'A' comes from
register 'R1', and a bit for the input variable 'B' comes from register 'R2'.
• The outcome produced by adding both input variables is stored into either
third register or to one of the source registers.
 Binary Adder-Subtractor
• A Binary Adder-Subtractor is a special type of circuit that is used to perform both
operations, i.e., Addition and Subtraction. The operation which is going to be used
depends on the values contained by the control signal.
• In Arithmetic Logical Unit, it is one of the most important components.
• To work with Binary Adder-Subtractor, it is required that we have knowledge of the
XOR gate, Full-Adder, Binary Addition, and subtraction.
For example, we will take two 4-bit binary numbers 'X' and 'Y' for the operation with
digits.
X0 X1 X2 X3 for X
Y0 Y1 Y2 Y3 for Y
Example:
We assume that we have two 3 bit numbers,
i.e., X=100 and Y=011, and feed them in Full-
Adder as an input. For K=1
X0 = 0 X1 = 0 X2 = 1 Y0⨁K=Y0' and Cin=k=1
Y0 = 1 Y1 = 1 & Y2 = 0 So,
S0 = X0+Y0'+Cin
For K=0:
Y0⨁K=Y0 and Cin=K=0 S0 = 0+0+1
So, from first Full-Adder S0=1 and C0=0
S0 = X0+Y0+Cin Similarly,
S0= 0+1+0 S1 = X1+Y1'+C0
S0=1 S1 = 0+0+0
C0=0 S1=0 and C1=0
Similarly, Similarly,
S1 = X1+Y1+C0 S2 = X2+Y2'+C1
S1 = 0+1+0 S2 = 1+1+0
S1=1 and C1=0 S2=0 and C2=0
Similarly, Thus,
S2 = X2+Y2+C1 X = 010 = 4
Y = 011 = 3
S2 = 1+0+0 Difference = 001 = 1
S2=1 and C2=0
Thus,
X= 100 =4
Y = 011 = 3
 Decimal or BCD Adder
The BCD-Adder is used in the computers and the calculators that perform arithmetic operation
directly in the decimal number system. The BCD-Adder accepts the binary-coded form of
decimal numbers. The Decimal-Adder requires a minimum of nine inputs and five outputs.

Thus to implement BCD Adder Circuit we require :

• 4-bit binary adder for initial addition
• Logic circuit to detect sum greater than 9 and
• One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is 1.
The logic circuit to detect sum greater than 9 can be determined by simplifying the boolean
expression of given BCD Adder Truth Table.
Truth Table

When to add six

Case 1) C’=1
2) Finding K map
of 10 to 15

K-Map

+
• The two BCD numbers, together
with input carry, are first added in
the top 4-bit binary adder to
produce a binary sum.
• When the output carry is equal to
zero (i.e. when sum ≤ 9 and Cout =
0) nothing (zero) is added to the
binary sum.
• When it is equal to one (i.e. when
sum > 9 or Cout = 1), binary 0110 is
added to the binary sum through
the bottom 4-bit binary adder.
• The output carry generated from
the bottom binary adder can be
ignored, since it supplies
information already available at
the output-carry terminal.
 Code converter
The Code converter is used to convert one type of binary code to another. There are
different types of binary codes like BCD code, gray code, excess-3 code, etc. Different
codes are used for different types of digital applications.
• Binary to BCD code converter
• BCD to Excess-3 code converter
• BCD to Gray code converter
• Gray code to Excess-3 code converter
Binary – BCD Convertor

From, above conversion table, we can write

SOP form for different bits of BCD code.

𝐵5
𝐵4
𝐵3
𝐵2
𝐵1
BCD to Excess-3 code converter

From the truth table, the

minterms are obtained for
each outputs(E3, E2, E1, E0).
E3 = ∑m(5, 6, 7, 8, 9),
E2 = ∑m(1, 2, 3, 4, 9),
E1 = ∑m(0, 3, 4, 7, 8),
E0 = ∑m(0, 2, 4, 6, 8,)
The combinational logic circuit for BCD code to Excess-3 code conversion is drawn from
the obtained boolean expressions.
BCD to Gray code converter
From the minterms of each output G3, G2, G1, G0, the karnaugh map is implemented to
simplify the function.
The code converter circuit for BCD to gray code is drawn as below from the obtained
expression.
Gray code to Excess-3 code converter
 The minterms of each output E3, E2, E1, E0 are plotted in the karnaugh map and is
simplified as below.

In the k-map shown above for E0 output, although 2 to 3 pairs of cells can be grouped,
all the minterms are marked as isolated cells to make simplification easier.
In the k-map shown above for E0 output, although 2 to 3 pairs of cells can be
grouped, all the minterms are marked as isolated cells to make simplification
easier.

Actual boolean expression obtained from the K-map for E0 output

From the obtained expression for E3, E2, E1, E0, the code converter circuit
for gray to excess-3 is drawn as below.
 Binary to Gray Code Converters

*Simplify 4-bit binary to gray code using K-Map

The 4-bit binary to gray code conversion table is as follows:
Decimal 4-bit Binary 4-bit Gray Code
Number Code The bits of 4-bit Gray code are
ABCD G1G2G3G4 considered as G4G3G2G1. Now from
0 0000 0000 the conversion table, consider ones
1 0001 0001 in particular column
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
The Karnaugh maps (K-maps) for G4, G3, G2, and G1 are as follows:
The bits of 4-bit Gray code are considered as G4G3G2G1. Now from the
conversion table,

𝐺1
𝐺2

𝐺3

𝐺4
 Decoder
The combinational circuit that change the binary information into 2 N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines
define the 2N-bit code for the binary information. In simple words, the Decoder performs
the reverse operation of the Encoder. At a time, only one input line is activated for
simplicity. The produced 2N-bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

2 to 4 line decoder:
 Truth Table:

Logical circuit of the above

expressions is given below:

The logical expression of the term Y0, Y0, Y2, and

Y3 is as follows:
Y3=E.A.B
Y2=E.A.B'
Y1=E.A'.B
Y0=E.A'.B'
3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder,
there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0,
A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E'
is set to 1, one of these four outputs will be 1. The block diagram and the truth table of the
3 to 8 line encoder are given below.

Block Diagram: Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Logical circuit of the above expressions is given
Y2=A0'.A1.A2'
below:
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2
 Implementation of 3 to 8 decoder using 2
to 4 decoders
Implement 3 to 8 decoder using 2 to 4 decoders. We know that 2 to 4 Decoder has two
inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3 to 8 Decoder has three inputs A2,
A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order decoders required for implementing higher
order decoder using the following formula.

Where, m1 = number of outputs of lower order decoder.

m2 = number of outputs of higher order decoder.
Here, m1 = 4 and m2 = 8. Substitute, these two values in the above formula.
We require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block
diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.
4 to 16 line Decoder

Let us implement 4 to 16 decoder using 3 to 8 decoders. We know that 3 to 8

Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to 16
Decoder has four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0
We know the following formula for finding the number of lower order decoders
required.

Substitute, m1 = 8 and m2 = 16 in the above formula.

 Binary decoders can be cascaded together to form a larger decoder circuit. Using two 2
input decoders, 4 input decoders can be constructed, by cascading each other. Similarly,
by cascading two 3 to 8 decoders, 4 to 16 binary decoders can be constructed. To design
the 4 to 16 decoders, 4 binary inputs(A0, A1, A2, A3) are needed. The three inputs A, B
and C are given as input to two 3 to 8 binary decoders. The fourth input D is given as
enable input(EN) to both decoders.
From the diagram when input A3 = 0, the decoder at the top will be enabled and that is
on the bottom will get disabled. When A3 = 1, it will enable the bottom decoder and
disable the top one.

Block Diagram:
Implementation of 4 to 16 decoder using 2
to 4 decoders
Truth Table:

The logical expression of

the term A0, A1, A2,…, A15
are as follows:
Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3
Logical circuit of the above expressions is :
BCD to Decimal Decoder or 4 to10 Decoder
Problem
*Implement full adder circuit with a decoder and two or
gates
Ans: From truth table of full adder
S(A,B,C)=
C(A,B,C)=
There are three inputs and 8 outputs so we need 3 to 8
decoder
Application of Decoder:

Some of the decoder application include

• Code converters.
• Used in the memory system of computers to access a particular
memory location based on the address produced by a computing
device.
• To carry out the operations in the Arithmetic Logic Unit of CPU,
decoders are used to decode the program instructions to activate the
control lines.
 ENCODER
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It
has maximum of 2n input lines and ‘n’ output lines. It will produce a binary code
equivalent to the input, which is active High. Therefore, the encoder encodes 2 n input
lines with ‘n’ bits. It is optional to represent the enable signal in encoders.

4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the following figure.
 Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as
8 to 3 line Encoder:
Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary
Encoder is shown in the following figure.

Inputs Outputs
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
From Truth table, we can write the Boolean functions for each output as
 Decimal to BCD Encoder

The Octal to Binary Encoder is also known as 10 to 4 line Encoder. In 10 to 4 line

encoder, there are total of ten inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, and Y9 and
four outputs, i.e., A0, A1, A2, and A3. In 10-input lines, one input-line is set to true at
a time to get the respective BCD code in the output side. The block diagram and the
truth table of the decimal to BCD encoder are given below.
Block Diagram:
The logical expression of the term A0, A1, A2, and A3 is as follows:
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
Logical circuit of the above expressions is given below:
Drawbacks of Encoder

Following are the drawbacks of normal encoder.

• When more than one inputs of the encoder is High and the output
is invalid.
• When all the inputs of the encoder is zero then output is zero and
also if Y0 input is high and output is zero i.e for two input
conditions are getting same outputs.

So, to overcome these difficulties, we should assign priorities to each

input of encoder. Then, the output of encoder will be the binary code
corresponding to the active High inputs, which has higher priority.
This encoder is called as priority encoder.
 Priority Encoder
4 to 2 line Priority Encoder:

In this priority encoder, there are total of 4 inputs, i.e., Y 0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. The Y3 has high and Y0 has low priority inputs. When more
than one input is '1' at the same time, the output will be the (binary) code
corresponding to the higher priority input. Below is the truth table of the 4 to 2 line
priority encoder.

Lowest Priority

Highest Priority
A1=Y3+Y2
A0=Y3+Y2'.Y1
 Multiplexers
A multiplexer is a combinational circuit that has 2n input lines and a single output line.
Simply, the multiplexer is a multi-input and single-output combinational circuit. The
binary information is received from the input lines and directed to the output line. On
the basis of the values of the selection lines, one of these data inputs will be connected
to the output.
Unlike encoder and decoder, there are n selection lines and 2 n input lines. So, there is a
total of 2N possible combinations of inputs. A multiplexer is also treated as Mux.
2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at
the selection line S0, one of these 2 inputs will be connected to the output.
The logical expression of the term Y is as follows:
Y=S0'.A0+S0.A1
4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection
lines, i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs
that are present at the selection lines S0 and S1, one of these 4 inputs are connected to
the output. The block diagram and the truth table of the 4×1 multiplexer are given
below.
The logical expression of the term Y is as follows:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4, A5, A6, and
A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the
combination of inputs that are present at the selection lines S 0, S1, and S2, one of these
8 inputs are connected to the output. The block diagram and the truth table of the 8×1
multiplexer are given below.
The logical expression of the term Y is as follows:
Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A
6+S0.S1.S3.A7
8 ×1 multiplexer using 4×1 and 2×1 multiplexer
Implement the 8×1 multiplexer using a lower order multiplexer. To implement the
8×1 multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1
multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has
only 1 selection line.
For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer
produces one output. So, in order to get the final output, we need a 2×1
multiplexer.
16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection
lines, i.e., S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S0, S1, and S2, one of these 16 inputs will
be connected to the output. The block diagram and the truth table of the 16×1
Y=A0.S0'.S1'.S2'.S3'+
A1.S0'.S1'.S2'.S3+
A2.S0'.S1'.S2.S3'+
A3.S0'.S1'.S2.S3+
A4.S0'.S1.S2'.S3'+
A5.S0'.S1.S2'.S3+
A6.S0'.S1.S2.S3'+
A7.S0'.S1.S2.S3+
A8.S0.S1'.S2'.S3'+
A9 .S0.S1'.S2'.S3+
A10.S0.S1'.S2.S3'+
A11.S0.S1'.S2.S3+
A12.S0.S1.S2'.S3'+
A13.S0.S1.S2'.S3+
A14.S0.S1.S2.S3'+
16×1 multiplexer using 8×1 and 2×1 multiplexer
We can implement the 16×1 multiplexer using a lower order multiplexer. To implement
the 8×1 multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1
multiplexer has 3 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only
1 selection line.
For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer
produces one output. So, in order to get the final output, we need a 2×1 multiplexer.
The block diagram of 16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.
 De-multiplexer
A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On the
basis of the values of the selection lines, the input will be connected to one of these
outputs. De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a
total of 2n possible combinations of inputs. De-multiplexer is also treated as De-mux.
1×2 De-multiplexer:
The logical expression of the term Y is as follows:
Y0=S0'.A
Y1=S0.A
1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S0 and S1, the input be connected to one of the
outputs. The block diagram and the truth table of the 1×4 multiplexer are given below.
The logical expression of the term Y is as follows:
Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A
1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6,
and Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S 0, S1 and S2, the input
will be connected to one of these outputs. The block diagram and the truth table of
the 1×8 de-multiplexer are given below.
The logical expression of the term Y is as follows:
Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A
1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer
We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To
implement the 1×8 de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-
multiplexer. The 1×4 multiplexer has 2 selection lines, 4 outputs, and 1 input. The 1×2
de-multiplexer has only 1 selection line.
1 x 16 De-multiplexer
In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S0, S1, and S2, the input will be connected to one
of these outputs. The block diagram and the truth table of the 1×16 de-multiplexer are
given below.
The logical
expression of the
term Y is as
follows:
Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y =A.S .S .S '.S
1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer
We can implement the 1×16 de-multiplexer using a lower order de-multiplexer. To
implement the 1×16 de-multiplexer, we need two 1×8 de-multiplexer and one 1×2
de-multiplexer. The 1×8 multiplexer has 3 selection lines, 1 input, and 8 outputs. The
1×2 de-multiplexer has only 1 selection line.