VHDL-Based Digital Design

Let’s Start Simple

• Support different description levels
– Structural (specifying interconnections of the gates),
– Dataflow (specifying logic equations), and
– Behavioral (specifying behavior)
Domains and Levels of Modeling
Structural Functional

high level of
abstraction

low level of
abstraction

“Y-chart” due to
Geometric Gajski & Kahn
Domains and Levels of Modeling
Structural Functional
Algorithm
(behavioral)

Register-Transfer
Language

Boolean Equation

Differential Equation

“Y-chart” due to
Geometric Gajski & Kahn
 Domains and Levels of Modeling
Structural Functional
Processor-Memory
Switch

Register-Transfer

Gate

Transistor

Geometric “Y-chart” due to

Gajski & Kahn
Domains and Levels of Modeling
Structural Functional

Polygons

Sticks

Standard Cells

Floor Plan

Geometric “Y-chart” due to

Gajski & Kahn
 VHDL Description of
Combinational Networks
 Entity-Architecture Pair

entity name port names port mode (direction)

port type punctuation

reserved words
VHDL Program Structure
4-bit Adder
4-bit Adder (cont’d)
4-bit Adder - Simulation
 Modeling Flip-Flops Using VHDL
Processes
General form of process

• Whenever one of the signals in the sensitivity list

changes, the sequential statements are executed
in sequence one time
D Flip-flop Model
Bit values are enclosed
in single quotes
JK Flip-Flop Model
JK Flip-Flop Model
Using Nested IFs and ELSEIFs
 VHDL Models for a MUX

Sel represents the integer

equivalent of a 2-bit binary
number with bits A and B

If a MUX model is used inside a process,

the MUX can be modeled using a CASE statement
(cannot use a concurrent statement):
 MUX Models (1)
architecture RTL1 of SELECTOR is
begin
library IEEE; p0 : process (A, SEL)
use IEEE.std_logic_1164.all; begin
use IEEE.std_logic_unsigned.all; if (SEL = "0000") then Y <= A(0);
entity SELECTOR is elsif (SEL = "0001") then Y <= A(1);
port ( elsif (SEL = "0010") then Y <= A(2);
elsif (SEL = "0011") then Y <= A(3);
A : in std_logic_vector(15 downto 0);
elsif (SEL = "0100") then Y <= A(4);
SEL : in std_logic_vector( 3 downto 0);
elsif (SEL = "0101") then Y <= A(5);
Y : out std_logic); elsif (SEL = "0110") then Y <= A(6);
end SELECTOR; elsif (SEL = "0111") then Y <= A(7);
elsif (SEL = "1000") then Y <= A(8);
elsif (SEL = "1001") then Y <= A(9);
elsif (SEL = "1010") then Y <= A(10);
elsif (SEL = "1011") then Y <= A(11);
elsif (SEL = "1100") then Y <= A(12);
elsif (SEL = "1101") then Y <= A(13);
elsif (SEL = "1110") then Y <= A(14);
else Y <= A(15);
end if;
end process;
end RTL1;
 MUX Models (2)
architecture RTL3 of SELECTOR is
• library IEEE; begin
• use IEEE.std_logic_1164.all; with SEL select
• use IEEE.std_logic_unsigned.all; Y <= A(0) when "0000",
A(1) when "0001",
• entity SELECTOR is
A(2) when "0010",
• port (
A(3) when "0011",
• A : in std_logic_vector(15 downto 0);
A(4) when "0100",
• SEL : in std_logic_vector( 3 downto 0); A(5) when "0101",
• Y : out std_logic); A(6) when "0110",
• end SELECTOR; A(7) when "0111",
A(8) when "1000",
A(9) when "1001",
A(10) when "1010",
A(11) when "1011",
A(12) when "1100",
A(13) when "1101",
A(14) when "1110",
A(15) when others;
end RTL3;
 MUX Models (3)
architecture RTL2 of SELECTOR is
• library IEEE; begin
• use IEEE.std_logic_1164.all; p1 : process (A, SEL)
• use IEEE.std_logic_unsigned.all; begin
• entity SELECTOR is case SEL is
when "0000" => Y <= A(0);
• port (
when "0001" => Y <= A(1);
• A : in std_logic_vector(15 downto 0); when "0010" => Y <= A(2);
• SEL : in std_logic_vector( 3 downto 0); when "0011" => Y <= A(3);
• Y : out std_logic); when "0100" => Y <= A(4);
• end SELECTOR; when "0101" => Y <= A(5);
when "0110" => Y <= A(6);
when "0111" => Y <= A(7);
when "1000" => Y <= A(8);
when "1001" => Y <= A(9);
when "1010" => Y <= A(10);
when "1011" => Y <= A(11);
when "1100" => Y <= A(12);
when "1101" => Y <= A(13);
when "1110" => Y <= A(14);
when others => Y <= A(15);
end case;
end process;
end RTL2;
 MUX Models (4)
• library IEEE;
• use IEEE.std_logic_1164.all; architecture RTL4 of SELECTOR is
• use IEEE.std_logic_unsigned.all; begin
• entity SELECTOR is Y <= A(conv_integer(SEL));
• port ( end RTL4;
• A : in std_logic_vector(15 downto 0);
• SEL : in std_logic_vector( 3 downto 0);
• Y : out std_logic);
• end SELECTOR;
Compilation and Simulation of VHDL Code

• Compiler (Analyzer) – checks the VHDL source code

– does it conforms with VHDL syntax and semantic rules
– are references to libraries correct
• Intermediate form used by a simulator or by a synthesizer
• Elaboration
– create ports, allocate memory storage, create interconnections, ...
– establish mechanism for executing of VHDL processes
 Timing Model
• VHDL uses the following simulation cycle to model the
stimulus and response nature of digital hardware

Start
Simulation Delay

Update Signals Execute

Processes

End
Simulation
 Delay Types
• All VHDL signal assignment statements prescribe an
amount of time that must transpire before the signal
assumes its new value
• This prescribed delay can be in one of three forms:
– Transport -- prescribes propagation delay only
– Inertial -- prescribes propagation delay and minimum input pulse
width
– Delta -- the default if no delay time is explicitly specified

Input Output
delay
 Transport Delay
• Transport delay must be explicitly specified
– I.e. keyword “TRANSPORT” must be used
• Signal will assume its new value after specified delay

-- TRANSPORT delay example

Output <= TRANSPORT NOT Input AFTER 10 ns;

Input Output

Input

Output

0 5 10 15 20 25 30
35
 Inertial Delay
• Provides for specification propagation delay and input
pulse width, i.e. ‘inertia’ of output:
target <= [REJECT time_expression] INERTIAL waveform;

• Inertial delay is default and REJECT is optional:

Output <= NOT Input AFTER 10 ns;
-- Propagation delay and minimum pulse width are 10ns

Input
Input Output

Output

0 5 10 15 20 25 30
35
 Inertial Delay (cont.)
• Example of gate with ‘inertia’ smaller than propagation delay
– e.g. Inverter with propagation delay of 10ns which suppresses pulses
shorter than 5ns

Output <= REJECT 5ns INERTIAL NOT Input AFTER 10ns;

Input

Output

• 0
Note: the REJECT feature5is new
10to VHDL
15 1076-1993
20 25 30
35
 Delta Delay
• Default signal assignment propagation delay if no delay is
explicitly prescribed
– VHDL signal assignments do not take place immediately
– Delta is an infinitesimal VHDL time unit so that all signal
assignments can result in signals assuming their values at a future
time
– E.g.

Output <= NOT Input;

-- Output assumes new value in one delta cycle
• Supports a model of concurrent VHDL process execution
– Order in which processes are executed by simulator does not
affect simulation output
Simulation Example
 Problem #1
entity not_another_prob is
• Using the labels, list port (in1, in2: in bit;
the order in which the a: out bit);
following signal end not_another_prob;
assignments are
evaluated if in2 architecture oh_behave of not_another_prob is
changes from a '0' to a signal b, c, d, e, f: bit;
'1'. Assume in1 has begin
been a '1' and in2 has L1: d <= not(in1);
been a '0' for a long L2: c<= not(in2);
time, and then at time L3: f <= (d and in2) ;
t in2 changes from a L4: e <= (c and in1) ;
'0' to a '1'. L5: a <= not b;
L6: b <= e or f;
end oh_behave;
 Problem #2
• Under what conditions do the two assignments below
result in the same behavior? Different behavior? Draw
waveforms to support your answers.

out <= reject 5 ns inertial (not a) after 20 ns;

out <= transport (not a) after 20 ns;
Modeling a Sequential Machine
Mealy Machine for
8421 BCD to 8421 BCD + 3 bit serial converter

How to model this in VHDL?

 Behavioral VHDL Model

Two processes:
• the first represents the combinational network;
• the second represents the state register
Simulation of the VHDL Model
Simulation command file:

Waveforms:
Dataflow VHDL Model

Q1 (t  ) Q2
Q2 (t  ) Q1
Q3 (t  ) Q1Q2 Q3  X ' Q1Q '3  X ' Q '1 Q '2
Z  X ' Q '3  XQ3
Structural Model

Package bit_pack is a part of library

BITLIB –
includes gates, flip-flops, counters
Simulation of the Structural Model
Simulation command file:

Waveforms:
 Wait Statements
• ... an alternative to a sensitivity list
– Note: a process cannot have both wait statement(s)
and a sensitivity list
• Generic form of a process with wait statement(s)
How wait statements work?
process • Execute seq. statement until
begin a wait statement is encountered.
sequential-statements • Wait until the specified condition is satisfied.
wait statement • Then execute the next
set of sequential statements until
sequential-statements
the next wait statement is encountered.
wait-statement • ...
... • When the end of the process is reached start
end process; over again at the beginning.
 Forms of Wait Statements
wait on sensitivity-list;
wait for time-expression;
wait until boolean-expression;

• Wait on • Wait until

– until one of the signals in the – the Boolean expression is
sensitivity list changes evaluated whenever one of the
• Wait for signals in the expression
– waits until the time specified by changes, and the process
the time expression has elapsed continues execution when the
expression evaluates to TRUE
– What is this:
wait for 0 ns;
Using Wait Statements (1)
Using Wait Statements (2)