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Wase 4

The document discusses CPU structure and function, focusing on processor organization, register organization, instruction cycles, and instruction pipelining. It covers various types of registers, their roles, and the importance of efficient instruction execution through techniques like pipelining and branch prediction. The document concludes with a summary of key concepts related to CPU organization and performance.

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purushotham
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8 views48 pages

Wase 4

The document discusses CPU structure and function, focusing on processor organization, register organization, instruction cycles, and instruction pipelining. It covers various types of registers, their roles, and the importance of efficient instruction execution through techniques like pipelining and branch prediction. The document concludes with a summary of key concepts related to CPU organization and performance.

Uploaded by

purushotham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 48

SEWP ZC413 Computer

Organization &
Architecture
Purushotham BV
Asst. Prof.
Department of CSE
DSCE, Bangalore – 78
94489 19064
[email protected]

01/24/25 CPU Structure & Function 1


Chapter 12

CPU Structure & Function

01/24/25 CPU Structure & Function 2


Objectives

 Processor Organization
 Register Organization
 Instruction Cycle
 Instruction Pipelining

01/24/25 CPU Structure & Function 3


CPU Structure

 CPU must:
 Fetch instructions

 Interpret instructions

 Fetch data

 Process data

 Write data

01/24/25 CPU Structure & Function 4


CPU With Systems Bus

01/24/25 CPU Structure & Function 5


CPU Internal Structure

01/24/25 CPU Structure & Function 6


Registers

 CPU must have some working space


(temporary storage)
 Called registers
 Number and function vary between processor
designs
 One of the major design decisions
 Top level of memory hierarchy

01/24/25 CPU Structure & Function 7


User Visible Registers

 General Purpose
 Data
 Address
 Condition Codes

01/24/25 CPU Structure & Function 8


General Purpose Registers

 May be true general purpose


 May be restricted
 May be used for data or addressing
 Data
 Accumulator
 Addressing
 Segment

01/24/25 CPU Structure & Function 9


General Purpose Registers
(Contd.,)
 Make them general purpose
 Increase flexibility and programmer options
 Increase instruction size & complexity
 Make them specialized
 Smaller (faster) instructions
 Less flexibility

01/24/25 CPU Structure & Function 10


How Many GP Registers?

 Between 8 - 32
 Fewer = more memory references
 More does not reduce memory references
and takes up processor real estate
 See also RISC

01/24/25 CPU Structure & Function 11


How big?

 Large enough to hold full address


 Large enough to hold full word
 Often possible to combine two data registers
 C programming

 double int a;

 long int a;

01/24/25 CPU Structure & Function 12


Condition Code Registers

 Sets of individual bits


 e.g. result of last operation was zero
 Can be read (implicitly) by programs
 e.g. Jump if zero
 Can not (usually) be set by programs

01/24/25 CPU Structure & Function 13


Control & Status Registers

 Program Counter
 Instruction Decoding Register
 Memory Address Register
 Memory Buffer Register

 Revision: what do these all do?

01/24/25 CPU Structure & Function 14


Program Status Word

 A set of bits
 Includes Condition Codes
 Sign of last result
 Zero
 Carry
 Equal
 Overflow
 Interrupt enable/disable
 Supervisor

01/24/25 CPU Structure & Function 15


Supervisor Mode

 Intel ring zero


 Kernel mode
 Allows privileged instructions to execute
 Used by operating system
 Not available to user programs

01/24/25 CPU Structure & Function 16


Other Registers

 May have registers pointing to:


 Process control blocks (see O/S)
 Interrupt Vectors (see O/S)

 N.B. CPU design and operating system


design are closely linked

01/24/25 CPU Structure & Function 17


Example Register
Organizations

01/24/25 CPU Structure & Function 18


Instruction Cycle with
Indirect
 May require memory
access to fetch
operands
 Indirect addressing
requires more
memory accesses
 Can be thought of as
additional instruction
subcycle

01/24/25 CPU Structure & Function 19


Instruction Cycle State
Diagram

01/24/25 CPU Structure & Function 20


Data Flow (Instruction
Fetch)
 Depends on CPU design
 In general:
 Fetch
 PC contains address of next instruction
 Address moved to MAR
 Address placed on address bus
 Control unit requests memory read
 Result placed on data bus, copied to MBR, then to IR
 Meanwhile PC incremented by 1

01/24/25 CPU Structure & Function 21


Data Flow (Data Fetch)

 IR is examined
 If indirect addressing, indirect cycle is
performed
 Right most N bits of MBR transferred to MAR
 Control unit requests memory read
 Result (address of operand) moved to MBR

01/24/25 CPU Structure & Function 22


Data Flow (Fetch Diagram)

01/24/25 CPU Structure & Function 23


Data Flow (Indirect Diagram)

01/24/25 CPU Structure & Function 24


Data Flow (Execute)

 May take many forms


 Depends on instruction being executed
 May include
 Memory read/write
 Input/Output
 Register transfers
 ALU operations

01/24/25 CPU Structure & Function 25


Data Flow (Interrupt)

 Simple
 Predictable
 Current PC saved to allow resumption after interrupt
 Contents of PC copied to MBR
 Special memory location (e.g. stack pointer) loaded to
MAR
 MBR written to memory
 PC loaded with address of interrupt handling routine
 Next instruction (first of interrupt handler) can be
fetched
01/24/25 CPU Structure & Function 26
Data Flow (Interrupt
Diagram)

01/24/25 CPU Structure & Function 27


Prefetch

 Fetch accessing main memory


 Execution usually does not access main
memory
 Can fetch next instruction during execution of
current instruction
 Called instruction prefetch

01/24/25 CPU Structure & Function 28


Improved Performance

 But not doubled:


 Fetch usually shorter than execution
 Prefetch more than one instruction?

 Any jump or branch means that prefetched


instructions are not the required instructions
 Add more stages to improve performance

01/24/25 CPU Structure & Function 29


Pipelining

 Fetch instruction (FI)


 Decode instruction (DI)
 Calculate operands (i.e. EAs) (CO)
 Fetch operands (FO)
 Execute instructions (EI)
 Write result (WR)
 Overlap these operations

01/24/25 CPU Structure & Function 30


Two Stage Instruction
Pipeline

01/24/25 CPU Structure & Function 31


Timing of Pipeline

01/24/25 CPU Structure & Function 32


Branch in a Pipeline

01/24/25 CPU Structure & Function 33


Six Stage
Instruction
Pipeline

01/24/25 CPU Structure & Function 34


Alternative
Pipeline
Depiction

01/24/25 CPU Structure & Function 35


Pipeline Performance

 The cycle time τ is the time needed to


advance a set of instructions one stage
through the pipeline
 Τ = max [τ ] + d = τ + d for 1≤ i ≤ k
i L m
where
Τm – max stage delay
k – no. of stages in the instruction pipeline
D – time delay of a latch, needed to advance
signals and data from one stage to the next

01/24/25 CPU Structure & Function 36


Pipeline Performance
(contd.,)
 The total time required Tk to execute all n
instructions is
Tk = [k+(n-1)] τ
 For the case discussed 14 = [6+(9-1)]
 The speed up factor Sk = T1/Tk
= nkτ / [k+(n-1)]τ
= nk / k+(n-1)

01/24/25 CPU Structure & Function 37


Speedup Factors with
Instruction Pipelining

01/24/25 CPU Structure & Function 38


Dealing with Branches

 Multiple Streams
 Prefetch Branch Target
 Loop buffer
 Branch prediction
 Delayed branching

01/24/25 CPU Structure & Function 39


Multiple Streams

 Have two pipelines


 Prefetch each branch into a separate pipeline
 Use appropriate pipeline

 Leads to bus & register contention


 Multiple branches lead to further pipelines
being needed

01/24/25 CPU Structure & Function 40


Prefetch Branch Target

 Target of branch is prefetched in addition to


instructions following branch
 Keep target until branch is executed
 Used by IBM 360/91

01/24/25 CPU Structure & Function 41


Loop Buffer

 Very fast memory


 Maintained by fetch stage
of pipeline
 Check buffer before
fetching from memory
 Very good for small loops
or jumps
 c.f. cache
 Used by CRAY-1
01/24/25 CPU Structure & Function 42
Branch Prediction
 Predict never taken
 Assume that jump will not happen
 Always fetch next instruction
 68020 & VAX 11/780
 VAX will not prefetch after branch if a page fault
would result (O/S v CPU design)
 Predict always taken
 Assume that jump will happen
 Always fetch target instruction

01/24/25 CPU Structure & Function 43


Branch Prediction (Contd.,)
 Predict by Opcode
 Some instructions are more likely to result in a
jump than thers
 Can get up to 75% success
 Taken/Not taken switch
 Based on previous history
 Good for loops
 Delayed Branch
 Do not take jump until you have to
 Rearrange instructions
01/24/25 CPU Structure & Function 44
Branch Prediction
Flowchart

01/24/25 CPU Structure & Function 45


Branch Prediction State
Diagram

01/24/25 CPU Structure & Function 46


Dealing With
Branches

01/24/25 CPU Structure & Function 47


Summary
 CPU Organization
 Register Organization
 Various register types
 Register Organization in 8086
 Instruction Cycle
 Instruction Pipeline
 Pipeline performance
 Dealing with branches

01/24/25 CPU Structure & Function 48

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