SEWP ZC413 Computer

Organization &
Architecture
Purushotham BV
Asst. Prof.
Department of CSE
DSCE, Bangalore – 78
94489 19064
[email protected]

01/24/25 Arithemtic 1
Chapter 9

Computer Arithmetic

01/24/25 Arithemtic 2
Objectives

 Integers and Real Numbers Representation

 Integer Arithmetic
 Floating Point Arithmetic
 IEEE Representation of Floating Point
Numbers

01/24/25 Arithemtic 3
 Arithmetic & Logic Unit
 Does the calculations
 Everything else in the computer is there to service
this unit
 Handles integers
 May handle floating point (real) numbers
 May be separate FPU (maths co-processor)
 May be on chip separate FPU (486DX +)

01/24/25 Arithemtic 4
ALU Inputs and Outputs

01/24/25 Arithemtic 5
Integer Representation
 Only have 0 & 1 to represent everything
 Positive numbers stored in binary
 e.g. 41=00101001
 No minus sign
 No period
 Sign-Magnitude
 One’s Compliment
 Two’s compliment

01/24/25 Arithemtic 6
Sign-Magnitude
 Left most bit is sign bit
 0 means positive
 1 means negative
 +18 = 00010010
 -18 = 10010010
 Problems
 Need to consider both sign and magnitude in arithmetic
 Two representations of zero (+0 and -0)

01/24/25 Arithemtic 7
One’s & Two’s Compliment

 +3 = 00000011
 +2 = 00000010
 +1 = 00000001
 +0 = 00000000
 -1 = 11111111
 -2 = 11111110
 -3 = 11111101

01/24/25 Arithemtic 8
Benefits

 One representation of zero

 Arithmetic works easily (see later)
 Negating is fairly easy
 3 = 00000011
 Boolean complement gives 11111100
 Add 1 to LSB 11111101

01/24/25 Arithemtic 9
Geometric Depiction of Twos
Complement Integers

01/24/25 Arithemtic 10
Negation Special Case 1

 0= 00000000
 Bitwise not 11111111
 Add 1 to LSB +1
 Result 1 00000000
 Overflow is ignored, so: - 0 = 0

01/24/25 Arithemtic 11
Negation Special Case 2
 -128 = 10000000
 bitwise not 01111111
 Add 1 to LSB +1
 Result 10000000
 So:
 -(-128) = -128 X
 Monitor MSB (sign bit)
 It should change during negation

01/24/25 Arithemtic 12
Range of Numbers

 8 bit 2s compliment
 +127 = 01111111 = 27 -1
 -128 = 10000000 = -27
 16 bit 2s compliment
 +32767 = 011111111 11111111 = 215 - 1
 -32768 = 100000000 00000000 = -2 15

01/24/25 Arithemtic 13
Conversion Between Lengths
 Positive number pack with leading zeros
 +18 = 00010010
 +18 = 00000000 00010010
 Negative numbers pack with leading ones
 -18 = 10010010
 -18 = 11111111 10010010
 i.e. pack with MSB (sign bit)

01/24/25 Arithemtic 14
Addition and Subtraction

 Normal binary addition

 Monitor sign bit for overflow
 Take twos compliment of subtrahend and add
to minuend
 i.e. a - b = a + (-b)
 So we only need addition and complement
circuits

01/24/25 Arithemtic 15
Hardware for Addition and
Subtraction

01/24/25 Arithemtic 16
N-bit adder / subtractor
yn - 1 y1 y0

Add/Sub
control

xn - 1 x1 x0

cn n-bit adder
c0

sn - 1 s1 s0

Figure 6.3. Binary addition-subtraction logic network.

01/24/25 Arithemtic 17
Multiplication
 Complex
 Work out partial product for each digit
 Take care with place value (column)
 Add partial products
 Methods
 Paper & Pencil Unsigned Muln.
 Shift & Add
 Booth’s Algorithm Signed Muln.
 Fast Multiplication or Bit – pair method

01/24/25 Arithemtic 18
Multiplication Example

1011 Multiplicand (11 dec)

x 1101 Multiplier (13 dec)
1011 Partial products
0000 Note: if multiplier bit is 1 copy
1011 multiplicand (place value)
1011 otherwise zero
10001111 Product (143 dec)
Note: need double length result

01/24/25 Arithemtic 19
Array Multiplier
x y pk(in)
cout cin
pk(out) x2 0 x1 0 x0 0
y0

0
y1
...
0
y2

... 0

...

p2m – 1 p2m – 2 p2m – 3 p2m – 4 p2 p1 p0

01/24/25 Arithemtic 20
Unsigned Binary
Multiplication
Shift and Add Method

01/24/25 Arithemtic 21
Execution of Example

01/24/25 Arithemtic 22
Flowchart for Unsigned
Binary Multiplication

01/24/25 Arithemtic 23
Multiplying Negative
Numbers
 This does not work!
 Solution 1
 Convert to positive if required
 Multiply as above
 If signs were different, negate answer
 Solution 2
 Booth’s algorithm
 Fast Multiplication

01/24/25 Arithemtic 24
Booth’s Algorithm

01/24/25 Arithemtic 25
Example of Booth’s
Algorithm

01/24/25 Arithemtic 26
Booth’s Algorithm

 Take the Booth’s Recoded Format of Q

0 010 110 01 11 01 011 00

0+1 -1+1 0 - 1 0 +1 0 0 - 1+1 - 1+1 0 - 1 0 0

Booth recoding of a multiplier.

01/24/25 Arithemtic 27
Booth recoding table

Multiplier version of multiplicand

Biti Biti-1 selected by bit
0 0 0M
0 1 +1M
1 0  1M
1 1 0M

Booth multiplier recoding table.

01/24/25 Arithemtic 28
Example 1

0 1 1 0 1 (+13) 01101
1 1 0 1 0 -6 0-1 +1-1 0
000 0000000
111 110011
000 01101
111 0011
000 000
111 0 1 1 0 0 1 0 - 78

01/24/25 Arithemtic 29
Example 2
 0101 (5) X 0110 (6)
 -------------
 0101 X +10-10
 --------------
 0 0 0 0 0 0 0 0 M X -1 = 2's compl of M
 1111011+ 1010
 000000++ 1
 0 0 1 0 1 + + + -----
 ---------------- 1011
 1 0 0 0 1 1 1 1 0 (30)

01/24/25 Arithemtic 30
Example 3

10101X01100
1 0 1 0 1 X +1 0 -1 0 0 (BRF of Q)
0000000000
000000000+
00001011+
0000000+
110101+
1 1 0 1 1 1 1 1 0 0 (0010000011 + 1=0010000100)
4 + 128 = 132

01/24/25 Arithemtic 31
1010 X 1010

01/24/25 Arithemtic 32
Booth recoded multipliers

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Worst-case
multiplier
+1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1

1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0
Ordinary
multiplier
0 -1 0 0 +1 - 1 +1 0 - 1 +1 0 0 0 -1 0 0

0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1
Good
multiplier
0 0 0 +1 0 0 0 0 -1 0 0 0 +1 0 0 -1

01/24/25 Arithemtic 33
Bit-Pair Recoding

 Let us pair the bits of Q to reduce the

number of PPs
 Select the legend 0 always to RHS of LSB of
Q
 If needed extend the sign bit to make pairs
 Select the multiplier bit for multiplication

01/24/25 Arithemtic 34
 Table of multiplier bits
i+1 bit ith bit i-1 bit Multiplier bit

0 0 0 0XM
0 0 1 +1 X M
0 1 0 +1 X M
0 1 1 +2 X M
1 0 0 -2 X M
1 0 1 -1 X M
1 1 0 -1 X M
1 1 1 0XM
01/24/25 Arithemtic 35
Example 1

1010 X 1010 0
-1 -2
00001100
000110++
----------------------
0 0 1 0 0 1 0 0 (36)

01/24/25 Arithemtic 36
Example 2

01010X10110
11 01 10 0

01/24/25 Arithemtic 37
Example 3

01/24/25 Arithemtic 38
Example 4

01/24/25 Arithemtic 39
Division

 More complex than multiplication

 Negative numbers are really bad!
 Based on long division

01/24/25 Arithemtic 40
Division of Unsigned Binary
Integers

00001101 Quotient
Divisor 1011 10010011 Dividend
1011
Partial 001110
1011
Remainders
001111
1011
Remainder

01/24/25 Arithemtic 41
Flowchart for Unsigned
Binary Division

01/24/25 Arithemtic 42
Longhand division

21 10101
13 274 1101 100010010
26 1101
14 10000
13 1101
1 1110
1101
1

01/24/25 Arithemtic 43
Circuit Arrangements for
Division
Shift left

an an - 1 a0 qn- 1 q0
A Dividend Q
Quotient
setting

n+1-bit Add/Subtract
adder
Control
sequencer

0 mn - 1 m0
Divisor M

01/24/25 Arithemtic 44
Division Algorithm

1. Load the divisor into M and Dividend into A,

Q (in twos Complement form)
2. Shift A, Q left 1 bit position
3. If M and A have the same signs, perform A
= A – M; otherwise A = A + M
4. If the sign of A is 0 the set Q0 to 1;
otherwise set Q0 to 0 and restore A
5. Repeat Steps 2 thru 4 for n times (n-bit)

01/24/25 Arithemtic 45
Division Algorithm (Contd.,)

6. The Remainder is in A and quotient in Q if

Divisor and dividend were the same sign;
otherwise quotient in Q in twos complement
form.
D=QXV+R
D – Dividend
Q- Quotient
V Divisor
R - Remainder

01/24/25 Arithemtic 46
Real Numbers
 Numbers with fractions
 Could be done in pure binary
 1001.1010 = 24 + 20 +2-1 + 2-3 =9.625
 Where is the binary point?
 Fixed?
 Very limited
 Moving?
 How do you show where it is?

01/24/25 Arithemtic 47
Floating Point
Sign bit

Biased
Exponent Significand or Mantissa

 +/- .significand x 2exponent

 Misnomer
 Point is actually fixed between sign
bit and body of mantissa
 Exponent indicates place value
(point position)

01/24/25 Arithemtic 48
Floating Point Examples

01/24/25 Arithemtic 49
Signs for Floating Point

 Mantissa is stored in 2s compliment

 Exponent is in excess or biased notation
 e.g. Excess (bias) 128 means
 8 bit exponent field
 Pure value range 0-255
 Subtract 128 to get correct value
 Range -128 to +127

01/24/25 Arithemtic 50
Normalization

 FP numbers are usually normalized

 i.e. exponent is adjusted so that leading bit (MSB) of
mantissa is 1
 Since it is always 1 there is no need to store it
 (c.f. Scientific notation where numbers are
normalized to give a single digit before the decimal
point
 e.g. 3.123 x 103)

01/24/25 Arithemtic 51
FP Ranges

 For a 32 bit number

 8 bit exponent
 +/- 2256  1.5 x 1077
 Accuracy
 The effect of changing lsb of mantissa
 23 bit mantissa 2-23  1.2 x 10-7
 About 6 decimal places

01/24/25 Arithemtic 52
Expressible Numbers

01/24/25 Arithemtic 53
IEEE 754

 Standard for floating point storage

 32 and 64 bit standards
 8 and 11 bit exponent respectively
 Extended formats (both mantissa and
exponent) for intermediate results

01/24/25 Arithemtic 54
IEEE 754 Formats

01/24/25 Arithemtic 55
FP Arithmetic +/-

 Check for zeros

 Align significands (adjusting exponents)
 Add or subtract significands
 Normalize result

01/24/25 Arithemtic 56
Decimal Floating-Point Add
and Subtract Examples

Operands Alignment Normalize & round

6.144 102 0.06144 104 1.003644 105
+9.975 104 +9.975 104 + .0005 105
10.03644 104 1.004 105

Operands Alignment Normalize & round

1.076 10-7 1.076 10-7 7.7300 10-9
-9.987 10-8 -0.9987 10-7 + .0005 10-9
0.0773 10-7 7.730 10-9

01/24/25 Arithemtic 57
Hardware Structure for Floating-
Point Add and Subtract
e1 e2 f1 f2
me me mf mf  Adders for
Exponent
subtractor
Swap exponents and
Sign
mf
significands
Alignment
|e1 e2 | me
mf
shifter
mf + rounding bits
 Shifters for
Subtract
alignment and
normalize
s1 Sign Significand
s2 computation adder/subtractor
FA/FS Sign

e1 e2
mf + rounding bits
 Multiplexers for
me me

Select
Lead zeros
counter exponent and
me
mz
Normalize
and round
swap of
Subtract
and bias
significands
mf

Lead zeros
me

sr er fr

01/24/25 Arithemtic
counter 58
FP Addition & Subtraction
Flowchart

01/24/25 Arithemtic 59
FP Arithmetic x/

 Check for zero

 Add/subtract exponents
 Multiply/divide significands (watch sign)
 Normalize
 Round
 All intermediate results should be in double
length storage

01/24/25 Arithemtic 60
Decimal Floating-Point
Examples for Multiply and
Divide
 Multiply fractions and add exponents

Sign, fraction & exponent Normalize & round

( -0.1403 10-3) -0.4238463 102
(+0.3021 106 ) -0.00005 102
-0.04238463 10-3+6 -0.4238 102

Divide fractions and subtract exponents
Sign, fraction & exponent Normalize & round
( -0.9325 102) +0.9306387 109
( -0.1002 10-6 ) +0.00005 109
+9.306387 102-(-6) +0.9306 109
01/24/25 Arithemtic 61
Floating Point Multiplication

01/24/25 Arithemtic 62
Floating Point Division

01/24/25 Arithemtic 63
Summary
 Integer Numbers
 S & M, 1’s & 2’s complement
 ADD/SUB
 Multiplication
 Paper & pencil
 Shift & Add
 Booth’s Algorithm
 Bit-pair technique

01/24/25 Arithemtic 64
Summary

 Division
 Restoration
 Non-Restoration
 Floating Point Representation
 FP Arithmetic
 H/w for Add & Subtract of Fp
 Rule for FP Arithmetic

01/24/25 Arithemtic 65
Chapter 10

Instruction Sets:
Characteristics and
Functions and Computer

01/24/25 Arithemtic 66
Objectives

 Machine Instruction Characteristics

 Types of Operands
 Types of Operations
 Assembly Language

01/24/25 Arithemtic 67
What is an instruction set?

 The complete collection of instructions that

are understood by a CPU
 Machine Code
 Binary
 Usually represented by assembly codes

01/24/25 Arithemtic 68
Elements of an Instruction
 Operation code (Op code)
 Do this
 Source Operand reference
 To this
 Result Operand reference
 Put the answer here
 Next Instruction Reference
 When you have done that, do this...

01/24/25 Arithemtic 69
Where have all the Operands
gone?
 Long time passing….
 (If you don’t understand, you’re too young!)
 Main memory (or virtual memory or cache)
 CPU register
 I/O device

01/24/25 Arithemtic 70
Instruction Cycle State
Diagram

01/24/25 Arithemtic 71
Instruction Representation
 In machine code each instruction has a unique bit
pattern
 For human consumption (well, programmers
anyway) a symbolic representation is used
 e.g. ADD, SUB, LOAD

 Operands can also be represented in this way

 ADD A,B

01/24/25 Arithemtic 72
Simple Instruction Format

01/24/25 Arithemtic 73
Instruction Types

 Data processing
 Data storage (main memory)
 Data movement (I/O)
 Program flow control

01/24/25 Arithemtic 74
Number of Addresses (a)

 3 addresses
 Operand 1, Operand 2, Result
 a = b + c;
 May be a forth - next instruction (usually implicit)
 Not common
 Needs very long words to hold everything

01/24/25 Arithemtic 75
Number of Addresses (b)

 2 addresses
 One address doubles as operand and result
 a=a+b
 Reduces length of instruction
 Requires some extra work
 Temporary storage to hold some results

01/24/25 Arithemtic 76
Number of Addresses (c)

 1 address
 Implicit second address
 Usually a register (accumulator)
 Common on early machines

01/24/25 Arithemtic 77
Number of Addresses (d)
 0 (zero) addresses
 All addresses implicit
 Uses a stack

 e.g. push a

 push b
 add
 pop c
c=a+b

01/24/25 Arithemtic 78
How Many Addresses
 More addresses
 More complex (powerful?) instructions
 More registers
 Inter-register operations are quicker
 Fewer instructions per program
 Fewer addresses
 Less complex (powerful?) instructions
 More instructions per program
 Faster fetch/execution of instructions

01/24/25 Arithemtic 79
Design Decisions (1)
 Operation repertoire
 How many ops?
 What can they do?
 How complex are they?
 Data types
 Instruction formats
 Length of op code field
 Number of addresses

01/24/25 Arithemtic 80
Design Decisions (2)

 Registers
 Number of CPU registers available
 Which operations can be performed on which
registers?
 Addressing modes (later…)

 RISC v CISC

01/24/25 Arithemtic 81
Types of Operand
 Addresses
 Numbers
 Integer/floating point
 Characters
 ASCII etc.
 Logical Data
 Bits or flags
 (Aside: Is there any difference between numbers
and characters? Ask a C programmer!)

01/24/25 Arithemtic 82
Specific Data Types
 General - arbitrary binary contents
 Integer - single binary value
 Ordinal - unsigned integer
 Unpacked BCD - One digit per byte
 Packed BCD - 2 BCD digits per byte
 Near Pointer - 32 bit offset within segment
 Bit field
 Byte String
 Floating Point

01/24/25 Arithemtic 83
Types of Operation

 Data Transfer
 Arithmetic
 Logical
 Conversion
 I/O
 System Control
 Transfer of Control

01/24/25 Arithemtic 84
Data Transfer
 Specify
 Source

 Destination

 Amount of data

 May be different instructions for different movements

 e.g. IBM 370

 Or one instruction and different addresses

 e.g. VAX

01/24/25 Arithemtic 85
Arithmetic

 Add, Subtract, Multiply, Divide

 Signed Integer
 Floating point ?
 May include
 Increment (a++)
 Decrement (a--)
 Negate (-a)

01/24/25 Arithemtic 86
Shift and Rotate Operations

01/24/25 Arithemtic 87
Logical

 Bitwise operations
 AND, OR, NOT

01/24/25 Arithemtic 88
Conversion

 E.g. Binary to Decimal

01/24/25 Arithemtic 89
Input/Output

 May be specific instructions

 May be done using data movement
instructions (memory mapped)
 May be done by a separate controller (DMA)

01/24/25 Arithemtic 90
Systems Control

 Privileged instructions
 CPU needs to be in specific state
 Ring 0 on 80386+
 Kernel mode
 For operating systems use

01/24/25 Arithemtic 91
Transfer of Control
 Branch
 e.g. branch to x if result is zero
 Skip
 e.g. increment and skip if zero
 ISZ Register1
 Branch xxxx
 ADD A
 Subroutine call
 c.f. interrupt call

01/24/25 Arithemtic 92
Branch Instruction

01/24/25 Arithemtic 93
Nested Procedure Calls

01/24/25 Arithemtic 94
Use of Stack

01/24/25 Arithemtic 95
Byte Order
(A portion of chips?)
 What order do we read numbers that occupy
more than one byte
 e.g. (numbers in hex to make it easy to read)
 12345678 can be stored in 4x8bit locations
as follows

01/24/25 Arithemtic 96
Byte Order (example)

 Address Value (1) Value(2)

 184 12 78
 185 34 56
 186 56 34
 186 78 12

 i.e. read top down or bottom up?

01/24/25 Arithemtic 97
Byte Order Names

 The problem is called Endian

 The system on the left has the least
significant byte in the lowest address
 This is called big-endian
 The system on the right has the least
significant byte in the highest address
 This is called little-endian

01/24/25 Arithemtic 98
Example of C Data Structure

01/24/25 Arithemtic 99
Alternative View of Memory
Map

01/24/25 Arithemtic 100

Standard…What Standard?
 Pentium (80x86), VAX are little-endian
 IBM 370, Moterola 680x0 (Mac), and most RISC
are big-endian
 Internet is big-endian
 Makes writing Internet programs on PC more awkward!
 WinSock provides htoi and itoh (Host to Internet & Internet
to Host) functions to convert

01/24/25 Arithemtic 101

Summary

 Elements of m/c Instruction

 3,2,1,0 and 11/2 Address machines
 Types of Operands
 Types of Operations
 Flow transfer & Procedures
 Assembly Language
 Little – and Big – Endian orders

01/24/25 Arithemtic 102