UNIT-2

Unit-II: Introduction to FPGAs

(SYLLABUS)
• Programmable Logic FPGA
• Configuration Logic Blocks
• Function Generator
• ROM Implementation
• RAM Implementation
• Time Skew Buffers
• FPGA Design Tools
• Network-on-chip
• Adaptive System-on-chip
• AES ASIC Implementation
• Advanced FPGA Design
 Programming Technology

Altera->Intel
Xilinx Actel -> Microsemi
 FPGAs and VLSI

 FPGAs are standard parts:

– Pre-manufactured.
– Don’t worry (much) about physical design.
 Custom silicon:
– Tailored to your application.
– Generally lower power consumption.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Standard parts vs. custom

 Do you build your system with an FPGA or with custom

silicon?
– FPGAs have shorter design cycle.
– FPGAs have no manufacturing delay.
– FPGAs reduce inventory.
– FPGAs are slower, larger, more power-hungry.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Advantages
Reconfigurable
Saves board space
Flexible to changes
No need for ASIC type expensive design and production
Fast time to market
Bugs can be fixed easily
Of the shelf solutions are available
 Challenges in system design

 Multiple levels of abstraction: logic to CPUs.

 Multiple and conflicting constraints: low cost and high
performance are often at odds.
 Short design time: Late products are often irrelevant.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 The system design process

 May be part of larger product design.

 Major levels of abstraction:
– specification;
– architecture; FPGA-based system design
– logic design;
– circuit design;
– layout.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Dealing with complexity

 Divide-and-conquer: limit the number of components you

deal with at any one time.
 Group several components into larger components:
– transistors form gates;
– gates form functional units;
– functional units form processing elements;
– etc.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Levels of abstraction

 Specification: function, cost, etc.

 Architecture: large blocks.
 Logic: gates + registers.
 Circuits: transistor sizes for speed, power.
 Layout: determines parasitics.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Top-down vs. bottom-up design

 Top-down design adds functional detail.

– Create lower levels of abstraction from upper levels.
 Bottom-up design creates abstractions from low-level
behavior.
 Good design needs both top-down and bottom-up efforts.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Design abstractions
English specification
Executable Throughput,
program behavior design time

register- Function units,

function Sequential clock cycles cost
transfer
machines
Literals,
Logic gates logic logic depth

transistors circuit nanoseconds

rectangles layout microns

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 FPGA design

 FPGA manufacturer creates an FPGA fabric; system

designer uses the fabric.
 FPGA fabric design issues:
– Study sample user designs.
– Select interconnect topology.
– Create logic element structures.
– Design circuits, layout.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Topics

 FPGA fabric architecture concepts.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Elements of an FPGA fabric

 Logic. IOB IOB IOB …

 Interconnect. LE LE LE
 I/O pins. interconnect

LE LE LE
…

LE LE LE

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Terminology
 Configuration: bits that determine logic function +
interconnect.
 CLB: combinational logic block = logic element (LE).
 LUT: Lookup table = SRAM used for truth table.
 I/O block (IOB): I/O pin + associated logic and electronics.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Logic element
 Programmable:
– Input connections.
– Internal function.
 Coarser-grained than logic gates.
– Typically 4 inputs.
 Generally includes register.
 May provide specialized logic.
– Adder carry chain.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Example logic element

 Lookup table: a b out

0 0 0 1

a 0010 0 1 0 0

memory out 1 0
b
1001 1 0
0 1

1 1

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Logic synthesis

 How do we break the function into logic elements?

 How do we implement an operation within a logic element?

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Placement

 Where do we put each piece of logic in the array of logic

elements?

LE LE LE

LE LE
… LE

LE LE LE

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Programmable wiring

 Organized into channels.

– Many wires per channel.
 Connections between wires made at programmable
interconnection points.
 Must choose:
– Channels from source to destination.
– Wires within the channels.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Programmable interconnection point

D Q

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Programmable wiring paths

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Choosing a path

LE

LE

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Routing problems

 Global routing:
– Which combination of channels?
 Local routing:
– Which wire in each channel?
 Routing metrics:
– Net length.
– Delay.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Segmented wiring

Length 1

Length 2

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Offset segments

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 I/O

 Fundamental selection: input, output, three-state?

 Additional features:
– Register.
– Voltage levels.
– Slew rate.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Programming technologies

 SRAM.
– Can be programmed many times.
– Must be programmed at power-up.
 Antifuse.
– Programmed once.
 Flash.
– Similar to SRAM but using flash memory.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Configuration

 Must set control bits for:

– LE
– Interconnect.
– I/O blocks.
 Usually configured off-line.
– Separate burn-in step (antifuse).
– At power-up (SRAM).

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Reconfiguration

 Some FPGAs are designed for fast configuration.

– A few clock cycles, not thousands of clock cycles.
 Allows hardware to be changed on-the-fly.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 FPGA fabric architecture questions

 Given limited area budget:

– How many logic elements?
– How much interconnect?
– How many I/O blocks?

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Logic element questions
 How many inputs?
 How many functions?
– All functions of n inputs or eliminate some combinations?
– What inputs go to what pieces of the function?
 Any specialized logic?
– Adder, etc.
 What register features?

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

 Interconnect questions

 How many wires in each channel?

 Uniform distribution of wiring?
 How should wires be segmented?
 How rich is interconnect between channels?
 How long is the average wire?
 How much buffering do we add to wires?

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

Configuration vs. programming
• FPGA configuration: • CPU programming:
• Bits stay at the device they program.
• Instructions are fetched
• A configuration bit controls a switch or a logic bit.a memory.
from
• Instructions select
complex operations.

add r1, r2 add IR

r1, r2
memory CPU
I/O block questions
• How many pins?
• Maximum number of pins determined by package type.
• Are pins programmed individually or in groups?
• Can all pins perform all functions?
• How many logic families do we support?
 Comparison
Flexibility
Processors
Instruction Flexibility
90% Area Overhead
(Cache , Predictions)

FPGA
Device-wide flexibility
99% Area Overhead
(Configuration)

ASIC
No Flexibility
20% Area Overhead
(Testing)

Speed , Power Efficiency

 Usages
Digital designs where ASIC is not commercial
Reconfigurable systems
Upgradeable systems
ASIC prototyping and emulation
Education
 Xilinx FPGAs

• Xilinx XC2000
• Xilinx XC3000
• Xilinx XC4000
 Configuration Memory Cell

XC2000: Logic Cell Array Structure

Input/Output Block (IOB)
Configurable Logic Block (CLB)
Configurable Logic Block (CLB)
CLB Combinatorial Block (D, Q can’t be used in the same function
CLB Storage Element
General Purpose Interconnect
Routing and Switch Matrix Connections
Longline Interconnect
XC2000 Longlines, I/O Clocks, I/O Direct Interconnect
Direct Interconnect
 Applications of CPLDs and
FPGAs
CPLDs and FPGAs are used today in many diverse applications:
• Consumer products like DVD players and high-end television
sets
• controller circuits for automobile factories and test equipment
• Internet routers and high-speed network switches
• computer equipment like large tape and disk storage systems
• CPLD
• when the needed circuit is not very large
• when the device has to perform its function immediately
upon application of power
• FPGAs are mainly volatile type.
• This property results  delay before the FPGA chip can
perform its function
 FPGA constraints…

• FPGAs are suitable for implementation of circuits over a large

range of size, from about 1000 to more than a million logic gates
• In addition to size , speed of operation, power dissipation, cost
etc. are considered
• When above are not met, other types of ASICs are used
 Special FPGA functions
Internal SRAM
Embedded Multipliers
and DSP blocks
Embedded logic analyzer
Embedded CPUs
High speed I/O (~10GHz)
DDR/DDRII/DDRIII SDRAM
interfaces
PLLs
 Usages
Digital designs where ASIC is not commercial
Reconfigurable systems
Upgradeable systems
ASIC prototyping and emulation
Education
Floating gate Avalanche injection MOS Transistor(FAMOS)
Programming (putting electrons into the floating gate means writing a 0
Erasing (removing the charge from the floating gate) means resetting the flash memory contents to 1;
or
a programmed cell stores a logic 0, an erased cell stores a logic 1.
Programming (putting electrons into the floating gate means writing a 0

Erasing (removing the charge from the floating gate)

means resetting the flash memory contents to 1;

OR

a programmed cell stores a logic 0, an erased cell stores a logic 1.

EPROM(UV Erasure)
FLOting gate Tunneling OXide(FLOTOX)
 Antifuses

 Permanently programmed.
 Make a connection with electrical signal.
– More reliable than breaking a connection.
– Avoids shrapnel.
 Resistance of about 100 W.

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR

Programmable low-impedance circuit element ( PLICE ) ANTIFUSE
ACTEL-FPGA
Metal–metal antifuse
 Antifuse structure

Metal 2
antifuse

via
Metal 1

substrate

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR

 Antifuse programming
 Need to be able to apply programming voltage to every
antifuse.
– Path from VDD to GND.
 Programming can be performed slowly.
– Don’t need a lot of parallelism.
 Use the wiring network to gain access to the antifuses.
– Access transistors control path to antifuse.

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR

 Antifuse programming access transistors

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR
 Flash-programmed FPGA

 Flash is electrically-erasable EPROM.

 Allows reprogramming without boot-up procedure.

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR

 Flash-programmed switch

FPGA-Based System Design: Chapter 3 Copyright  2003 Prentice Hall PTR

 Commercial FPGA Companies List-- Partial

• Xilinx and Altera

• Lattice Semiconducto
• Microsemi(previously Actel)
• SiliconBlue Technologies
• Achronix
• QuickLogic
• e2v
• Atmel
 REVIEW QUESTIONS

1. What are the main parts in an FPGA?

2. What are the different types of Programming technologies?
3. Applications of FPGA?
4. Advantages of FPGA?
5. Working of ROM, DRAM,SRAM,EPROM,EEPROM
6. How any logic is implemented in Xilinx FPGA?
7. Compare designing using general purpose processors, ASIC & FPGA?
8. How MPGA design is different from FPGA design?
9. What are the different levels of abstraction? Importance of RTL?
10. FPGA disadvantages?
11. Commercially available FPGAs
 REVIEW QUESTIONS contd….
12. What is function generator block made up of?
13. Define setup time and hold time of a FF
14. What is the difference between FF and Latch?
15. Define clock skew?
16. What are its effects of skew on the propagation delay of comb. logic?
17. What are SoCs made up of?
18. Compare soft IP and hard IP cores.
19. What is adaptive SoC?
20. What are the problems in bus architectures? How to overcome them?
21. What is symmetric key cryptography? What are the rounds in AES
algorithm?