Electrical

Engineering

Islamabad

EEE241
Digital Logic Design
Lecture No. 4
Dr. Riaz Hussain
Assistant Professor
Department of Electrical Engineering
COMSATS Institute of Information Technology, Islamabad
 Review
• What is the utility of k Maps?
• For a 6 variable k Map, how many square boxes will be required?
• What is the rule for two adjacent squares in k-maps?
• What is the rule for combining the squares? i.e. rule for size of any set?
• What are implicants, prime implicants and essential prime implicants? What is the
rule for getting the minimized expression?
• How do we get the expression for a complement of a function from the k-map?
• What is the advantage of considering don’t care condition?
• Which gates are called universal gates?
• Why NAND and NOR gates are preferred?
• Any circuit can be implemented using NAND only gates? (T/F)
• Why XOR is called an Odd Function?
• Does XOR hold Commutative property?
• Can you make an even parity generator and checker?

01/23/2025 Dr. Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 2

 Outline
• Introduction to combinational logic
• Combinational circuits
• Analysis procedure
• Design procedure
• Binary adder-subtractor
• Decimal adder
• Binary multiplier
• Magnitude comparator
• Decoders
• Encoders
• Multiplexers
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 3
 Must Reading
• Chapter No. 4: Combinational Logic

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 4

 Introduction
• Logic circuits
– Combinational
• Only logic gates
• Output depends only on present combination of inputs
• Can be specified logically by a set of Boolean functions
– Sequential
• Logic gates and also storage elements
• Outputs are function of inputs and state of the storage
elements

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 5

 Combinational Circuits
• Output is function of input only
i.e. no feedback

Combinational
n inputs •
•
•
•
m outputs
• Circuits •


When input changes, output may change (after a
delay)
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 6
 Combinational Circuits
• Analysis
– Given a circuit, find out its function ?
A
B
F1
C
A
B
C
A

– Function may be expressed as:

B

A
C

B
F2
?
C

• Boolean function
• Truth table
• Design
– Given a desired function, determine its circuit
– Function may be expressed as:
• Boolean function
?
• Truth table

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 7

 Analysis Procedure
• Boolean Expression Approach
A
B
F1
C ABC
A A+B+C
B AB'C'+A'BC'+A'B'C
C
A
B (A’+B’)(A’+C’)(B’+C’)

A
F2
C
AB+AC+BC
B
C F1=AB'C'+A'BC'+A'B'C+ABC
01/23/2025 Riaz Hussain ([email protected])
F2=AB+AC+BC
CIIT-IBD-EE EEE241 DLD Lecture-04 8
 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=0 0 0 0 0 0
B=0 0 0
F1
C= 0
A=0 0
B=0 0
C= 0
0 1
A=0
B=0
0
A=0 0
F2
C= 0
0
B=0
C= 0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 9

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=0 0 0 0 0 0
B=0 0 1
F1 0 0 1 1 0
C= 1
A=0 1
B=0 1
C= 1
0 1
A=0
B=0
0
A=0 0
F2
C= 1
0
B=0
C= 1

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 10

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=0 0 0 0 0 0
B=1 0 1
F1 0 0 1 1 0
C= 0
A=0
0 1 0 1 0
1
B=1 1
C= 0
0 1
A=0
B=1
0
A=0 0
F2
C= 0
0
B=1
C= 0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 11

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=0 0 0 0 0 0
B=1 0 0
F1 0 0 1 1 0
C= 1
A=0
0 1 0 1 0
1
B=1 0 0 1 1 0 1
C= 1
0 0
A=0
B=1
0
A=0 1
F2
C= 1
1
B=1
C= 1

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 12

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=1 0 0 0 0 0
B=0 0 1
F1 0 0 1 1 0
C= 0
A=1
0 1 0 1 0
1
B=0 1 0 1 1 0 1
C= 0 1 0 0 1 0
0 1
A=1
B=0
0
A=1 0
F2
C= 0
0
B=0
C= 0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 13

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=1 0 0 0 0 0
B=0 0 0
F1 0 0 1 1 0
C= 1
A=1
0 1 0 1 0
1
B=0 0 0 1 1 0 1
C= 1 1 0 0 1 0
0 0
A=1 1 0 1 0 1
B=0
1
A=1 1
F2
C= 1
0
B=0
C= 1

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 14

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=1 0 0 0 0 0
B=1 0 0
F1 0 0 1 1 0
C= 0
A=1
0 1 0 1 0
1
B=1 0 0 1 1 0 1
C= 0 1 0 0 1 0
1 0
A=1 1 0 1 0 1
B=1
0 1 1 0 0 1
A=1 1
F2
C= 0
0
B=1
C= 0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 15

 Analysis Procedure
• Truth Table Approach A B C F1 F 2
A=1 0 0 0 0 0
B=1 1 1
F1 0 0 1 1 0
C= 1
A=1
0 1 0 1 0
1
B=1 0 0 1 1 0 1
C= 1 1 0 0 1 0
1 0
A=1 1 0 1 0 1
B=1
1 1 1 0 0 1
A=1 1
C= 1
F2 1 1 1 1 1
1
B=1
C= 1 B B

0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 16
 Design Procedure
• Given a problem statement:
– Determine the number of inputs and outputs
– Derive the truth table
– Simplify the Boolean expression for each output
– Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

 4-bits  4-bits
 0-9
?  Value+3
values
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 17
 Design Procedure
• BCD-to-Excess 3 Converter
C C
A B C D w x y z 1 1 1
0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 1 0 1 0 0 x x x x B x x x x B
0 0 1 0 0 1 0 1 A 1 1 x x A 1 x x
0 0 1 1 0 1 1 0 D D
0 1 0 0 0 1 1 1
w = A+BC+BD x = B’C+B’D+BC’D’
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1 C C
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 1 1 1 1
1 1 1 1
1 0 0 1 1 1 0 0 B
x x x x x x x x B
1 0 1 0 x x x x A 1 A 1
x x x x
1 0 1 1 x x x x
D D
1 1 0 0 x x x x
1 1 0 1 x x x x y = C’D’+CD z = D’
1 1
01/23/2025
1 0 x x x x 18
Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04
1 1 1 1 x x x x
 Design Procedure
• BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
0 1 0 1 1 0 0 0 B

0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1
01/23/2025 1 1 Hussain
Riaz x x ([email protected])
x x CIIT-IBD-EE EEE241 DLD Lecture-04 19
 Seven-Segment Decodera
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
d g
0 0 1 0 1101101 y ? e
0 0 1 1 1111001 f
z g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx 1 1 1
x x x x x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx
z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD d = . . . Lecture-04 20
 Binary Adder
• Half Adder x S
y
HA
– Adds 1-bit plus 1-bit C

– Produces Sum and Carry x

+ y
x y ───
C S
C S
0 0 0 0
0 1 0 1
x S
1 0 0 1
1 1 1 0
C
y

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 21

 Binary Adder
• Full Adder x
y S
z FA
– Adds 1-bit plus 1-bit plus 1-bit C

– Produces Sum and Carry x

+ y
x y z y + z
C S
0 0 0 0 0 0 1 0 1 ───
0 0 1 0 1 x 1 0 1 0 C S
0 1 0 0 1 z
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
1 0 1 1 0 0 0 1 0
1 1 0 1 0 x 0 1 1 1
1 1 1 1 1 z
C = xy + xz + yz
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 22
 Binary Adder
• Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C z
z
y
z

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 23

 Binary Adder
• Full Adder
x S
y HA HA

z C

x
S

y
C

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 24

 Binary Adder
x3 x2 x 1 x0 y 3y 2y 1y 0
c3 c 2 c 1 .
+ x3 x2 x1 x0
Carry
Cy Binary Adder C0 + y 3 y2 y1 y0
Propagate
Addition ────────
Cy S3 S2 S1 S0
S 3S 2S 1S 0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
01/23/2025
S S
Riaz 3Hussain ([email protected])
2 CIIT-IBD-EE
S 1 DLD
EEE241
S 0
Lecture-04 25
 Binary Adder
• Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

CPA
Cy C0 CPA
Cy C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S1 S0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 26

 BCD Adder
• 4-bits plus 4-bits + x3 x2 x1 x0
+ y 3 y2 y1 y0
• Operands and Result: 0 to 9 ────────
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Cy S3 S2 S1 S0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0

0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0

1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0

9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Wrong BCD Value

01/23/2025 27
0001
Riaz Hussain ([email protected]) 1000 EEE241 DLD
CIIT-IBD-EE Lecture-04
 BCD Adder
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16 
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17 
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18 
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19 
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20 
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21 
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22 
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23 
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24 

+6

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 28

 BCD Adder
• Correct Binary Adder’s Output (+6)
– If
– the result is between ‘A’ and ‘F’
– Cy = 1
S3 S2 S1 S0 Err
S1
0 0 0 0 0

1 0 0 0 0 S2
1 1 1 1
1 0 0 1 0 S3 1 1
1 0 1 0 1
S0
1 0 1 1 1
1 1 0 0 1
Err = S3 S2 + S3 S1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 29
 BCD Adder
x3 x2 x1 x0 y3 y 2 y 1 y0

A3 A 2 A1 A0 B3 B2 B 1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Err

0 0

A 3 A2 A1 A 0 B3 B 2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Cy S3 S2 S1 S0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 30
 Binary Subtractor
• Use 2’s complement with binary adder
x – y = x + (-y) = x + y’ + 1
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 31

 Binary Adder/Subtractor
• M: Control Signal (Mode)
M=0  F = x + y x3 x2 x1 x0 y3 y2 y1 y0 M
M=1  F = x – y

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F 1 F0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 32

 Overflow
• Unsigned Binary Numbers
x x 3 2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

Carry C4 C3 C2 C1
• 2’s Complement Numbers S3 S2 S1 S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

Overflow C4
S3
C3
S2
C2
S1
C1
S0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 33
 Magnitude Comparator
• Compare 4-bit number to 4-bit number
3 Outputs: < , = , >
Expandable to more number of bits

x3  A3 B3  A3 B3 A3A2A1A0 B3B2B1B0
x2  A2 B2  A2 B2
Magnitude
x1  A1 B1  A1 B1 Comparator
x0  A0 B0  A0 B0
A<B A=B A>B
( A B )  x3 x2 x1 x0
( A  B )  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
( A  B )  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 34
 A3
Magnitude Comparator
x3

B3

A2
x2

B2

A1 (A<B)
x1

B1

A0
x0 (A>B)

B0
(A=B)
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 35
 Magnitude Comparator
x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
Magnitude Magnitude
1 I(A=B) I(A=B)
Comparator Comparator
0 I(A<B) I(A<B)
A<B A=B A>B A<B A=B A>B

A<B A=B A>B

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 36

 Decoders
• Extract “Information” from the code Only one
• Binary Decoder lamp will
turn on
– Example: 2-bit Binary Number

1
x1 0 0
Binary
0 0
x0 Decoder
0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 37

 Decoders
• 2-to-4 Line Decoder Y3

y3 Y2

Decoder
I1 Binary
y2
Y1
y1
I0
y0 Y0

I1 I 0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 I1 I 0 Y2 I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 I1 I 0 Y0 I1 I 0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 38
 Decoders
• 3-to-8 Line Decoder Y7  I 2 I1 I 0
Y6  I 2 I1 I 0
Y7 Y5  I 2 I1 I 0
Y6
Y4  I 2 I1 I 0
Y5
Decoder

I2
Binary

Y4 Y3  I 2 I1 I 0
I1
Y3 Y2  I 2 I1 I 0
I0
Y2
Y1  I 2 I1 I 0
Y1
Y0 Y0  I 2 I1 I 0

I2
I1
I0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 39
 Decoders
• “Enable” Control Y3

Y3 Y2

Decoder
I1
Binary Y2
I0
Y1 Y1
E
Y0
Y0
E I1 I 0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
1 0 1 0 0 1 0 E

1 1 0 0 1 0 0
1 1 1 1 0 0 0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 40
 Decoders
• Expansion I2 I 1 I 0
I2 I 1 I 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0
Y6

Binary
0 1 0 0 0 0 0 0 1 0 0 Y2
I1
0 1 1 0 0 0 0 1 0 0 0 Y1 Y5
1 0 0 0 0 0 1 0 0 0 0 E
Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3

Decoder
1 1 1 1 0 0 0 0 0 0 0 I0

Binary
Y2 Y3
I1
Y1 Y2
E
Y0 Y1
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04
Y410
 Decoders
• Active-High / Active-Low
I1 I0 Y3 Y2 Y1 Y0 I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y3 Y3 Y1
Decoder

I1 I1 Decoder
Binary

Binary
Y2 Y2 Y0

Y1 Y1
I0 I0 I1
Y0 Y0 I0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 42

 Implementation Using Decoders
• Each output is a minterm Binary
Decoder
• All minterms are produced
Y7
• Sum the required minterms
Y6
Y5
x I2
Example: Full Adder Y4
y I1
z Y3
S(x, y, z) = ∑(1, 2, 4, 7) I0
Y2
C(x, y, z) = ∑(3, 5, 6, 7) Y1
Y0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD S C

Lecture-04 43
 Implementation
Binary
Using
Binary
Decoders
Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 x I2
Y4 Y4
y I1 y I1
z Y3 z Y3
I0 I0
Y2 Y2
Y1 Y1
Y0 Y0

S C
S C
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 44
 Encoders
• Put “Information” into code Only one
• Binary Encoder switch
should be
– Example: 4-to-2 Binary Encoder activated
at a time
x1
x3 x2 x1 y1 y0
y1 0 0 0 0 0
x2 Binary
0 0 1 0 1
Encoder
y0 0 1 0 1 0
x3 1 0 0 1 1

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 45

 Encoders
• Octal-to-Binary Encoder (8-to-3) I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
0 0 0 0 0 0 0 1 0 0 0

Encoder
I5 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1
I4 Y1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1 I3 Y0
0 0 0 1 0 0 0 0 1 0 0 I2
0 0 1 0 0 0 0 0 1 0 1 I1
0 1 0 0 0 0 0 0 1 1 0 I0
1 0 0 0 0 0 0 0 1 1 1 I7
I6 Y2
I5
Y2 I 7  I 6  I 5  I 4 I4
I3 Y1
Y1 I 7  I 6  I 3  I 2 I2
I1
Y  I 7  I 5  I 3  I1
0
01/23/2025
I0 Y0
46
Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04
 Priority Encoders
• 4-Input Priority Encoder
I3 V

Encoder
I3 I 2 I 1 I 0 Y1 Y0 V

Priority
I2 Y1
0 0 0 0 0 0 0
I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 I 3  I 2 Y1
1 1 1 1
I2 Y0 I 3  I 2 I1
I3
1 1 1 1
I0 V
1 1 1 1 V  I 3  I 2  I1  I 0
I0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 47
 Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2
I4 Y4
Y1 I1
I3 Y3
Y0 I0
I2 Y2
I1 Y1
I0 Y0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 48

 Multiplexers

S1 S0 Y
I0
0 0 I0 I1
I1 MUX Y
0 1 I2
1 0 I2 I3 S1 S0
1 1 I3
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 49
 Multiplexers
• 2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
• 4-to-1 MUX I0

I1
Y
I0 I2

I1 I3
MUX Y
I2
I3 S1 S0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE
S1 S0
EEE241 DLD Lecture-04 50
 Multiplexers
• Quad 2-to-1 MUX A 3
Y3
A2
x3 I0 Y2
y3 MUX Y A1
I1 S Y1
A0
Y0
x2 I0
MUX Y
B3
y2 I1 S B2
A3
B1 A2
I0 A1 Y3
MUX Y B0
A0
I1 S Y
MUX 2
x1 B3 Y1
y1 S E B2 Y0
I0
MUX Y B1
I1 S B0 S E

S
x
01/23/2025
0 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 51
 Multiplexers
• Quad 2-to-1 MUX
A3
Y3 A3
A2
Y2 A2
A1
Y1 A1 Y3
A0
A0
MUX Y2
Y0
B3
B3 Y1
B2
B2 Y0
B1
B1
B0
B0 S E
Extra
Buffers
01/23/2025S ERiaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 52
 Implementation Using Multiplexers
• Example
F(x, y) = ∑(0, 1, 3)
x y F
1 I0
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3 S1 S0
1 1 1
x y

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 53

 Implementation Using Multiplexers
• Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F
1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3 MUX Y F
0 1 0 1 0
I4
0 1 1 0 0
1 I5
1 0 0 0 I6
1
1 0 1 0 SI2 7S1 S0
1 1 0 1
1 1 1 1 x y z
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 54
 Implementation Using Multiplexers
• Example
F(x, y, z) = ∑(1, 2, 6, 7)
x y z F
0 0 0 0 z I0
0 0 1 1 F=z z I1
F
MUX Y
0 1 0 1 0 I2
0 1 1 0 F=z 1 I3 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 55
 Implementation Using Multiplexers
• Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0 D I1
0 0 1 1 1 F=D D
0 1 0 0 1
I2
F=D 0
0 1 0 1 0 I3 MUX Y F
0 1 1 0 0 0
0 1 1 1 0 F=0 I4
1 0 0 0 0
D
1 0 0 1 0 F=0 1 I5
1 0 1 0 0
F=D 1 I6
1 0 1 1 1
1 1 0 0 1 SI2 7S1 S0
1 1 0 1 1
F=1
1 1 1 0 1
1 1 1 1 1 F=1 A B C
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 56
 Multiplexer Expansion
• 8-to-1 MUX using Dual 4-to-1 MUX
I0 I0
I1 I1
MUX Y
I2 I2
I3 I3 S1 S0
I0
MUX Y Y
I1
I0 S
I4 I1
I5 MUX Y
I2
I6 I3 S1 S0
I7
1 0 0
01/23/2025 S2 S([email protected])
Riaz Hussain 1 S0 CIIT-IBD-EE EEE241 DLD Lecture-04 57
 DeMultiplexers
Y3
Y2
I DeMUX
Y1
S1 S0 Y0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 58
 Multiplexer / DeMultiplexer Pairs
MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y Y4
I
I3 Y3
I2 Y2
I1 Y1
Y0
SI2 0S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 59
 DeMultiplexers / Decoders
Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX I0
Y1 Y1
E
S1 S0 Y0 Y0

E I1 I 0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 60

 Three-State Gates
• Tri-State Buffer
C A Y
0 x Hi-Z
A Y
1 0 0
1 1 1
C
• Tri-State Inverter A Y

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 61

 Three-State Gates
C D Y
A
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?

Not Allowed
D
A
C A if C = 1
Y= B if C = 0

B
01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 62
 Three-State Gates
I3

I2
Y
I1

I0
Y3
Decoder

S1 I1
Binary

Y2
S0 I0
Y1
E E
01/23/2025 Riaz Hussain ([email protected])
Y 0
CIIT-IBD-EE EEE241 DLD Lecture-04 63
 Recommended Reading
• http
• Acknowledgement and References:
– Chapter No. 4: Combinational Logic
– These slides are obtained from Princess Sumaya University, Computer Engineering
Department Course 4241-Digital Logic Design

01/23/2025 Riaz Hussain ([email protected]) CIIT-IBD-EE EEE241 DLD Lecture-04 64