LINT

What is Linting:

Linting is a process of static code analysis of the RTL design to check the
quality of the code using thousands of guidelines/rules based on good
coding practises.

Provides an insight into RTL code at an early stage in the design cycle.
 What is the main objective of linting
• To come up with clean RTL before proceeding to the backend stages of
ASIC design cycle.
• To reduce the synthesis errors ,simulation synthesis mismatch
issues,connectivity issues etc.

Lint Tools from different EDA companies:

1.Spyglass from synopsys
2.Gasper gold from cadence
3.Alint pro from ALDEC
4.Questa_auto check from mentor
5.HDL designer(built-in) from mentor
 LINT INPUTS
• RTL(.v & .SV)
• Waiver files(.awl) /.swl
• (.awl- alternative web language)
• Lib files
 RULES IN SPYGLASS LINT

Array Rules Latch Rules

Case Rules Instance Rules
Reset Rules Synthesis Rules
Clock Rules Expression Rules
Usage Rules Multiple driver Rules
Tristate Rules Simulation Rules
Assign Rules Event Rules
Function task Rules Loop Rules
Delay Rules Elab Rules
 LINT TARGETS
• Unsynthesizable constucts
• Unintentional latches
• Unused declarations
• Multiple drivers and undriven signals
• Race conditions
• Incorrect usage of blocking and non-blocking assignments
• Case statement style issues
• Set reset conflicts
• Out of range index
 EXAMPLE-1
module example1(a,b,c); Compile doesn’t generate any warning for
input a; this example

input b;
In this example ,by default the o/p c is a
output c; wire.It is not needed to declare it as wire.
assign c=a+b;
endmodule But some synthesis tools may need it to be
declared as wire.

If lint tool is applied on the code before

synthesis it points the above mistake.
 EXAMPLE-2
module example2(out,in); In this example spyglass lint
output[1:0] out; reports a violation because all
input[2:0] in; elements of the array in are not
assign out=in[1:0]; read.
endmodule

W111:All elements of the array are not read

 EXAMPLE-3

always@(in1,in2,in3,mem) In this example case 2’b10 clause is

begin missing and default is also not
case(in3) specified
2’b00:out[0]=inIImem[0];
2’b01:out[1]=in2&&mem[1];
2’b11:out[2]=in2&&mem[3];
endcase
end

W69:Ensure that a case statement specifies all possible cases and

has a default clause
 EXAMPLE-4
always@(posedge sclk1 or posedge srst1) • When both polarites of
begin set/reset signal are used,one
if(srst1) logic block always remains in
Q1<=2’b11; set/reset state.
else • If set/reset is high,the logic that
Q1<=din[1:0]; operates on positive set/reset
end will get set/reset.
always@(posedge sclk1 or negedge srst1) • If set/reset is low the logic that
begin operates on negative set/reset
if(!srst1) will get set/reset.
Q2<=2’b11; • The usage leads to mutually
else exclusive blocks of logic.
Q2<=din[1:0];
end

W392:Reports set/reset signal used with both polarites(positive and

negative)
 EXAMPLE-5
always@(posedge clk1 or posedge rst1)
In this example rst1 is used as a
begin
synchronous as well as asynchronous
if(rst1)
reset
out1<1’b0;
else
out1<=in;
end
always@(posedge clk1)
begin
if (rst1)
out2<=1’b0;
else
out2<=in;
end

W448:Set/reset is used both synchronous and asynchronous

 EXAMPLE -6
module example6(out1,out2,in1,in2,clk);
As a result of using both the edges of
input in1,in2,clk;
output reg out1,out2;
the clock behaviour of the module
always@(posedge clk) gets dependant on duty cycle of the
begin clock
out1<=in1;
end
always@(negedge clk)
begin
out2<=in2;
end
endmodule

W391:Reports modules driven by both edges of clock

 EXAMPLE-7
module example 7(out1,in1,clk);
Reading an uninitialized value
input clk;
may result in undriven nets post
input[2:0]in1;
synthesis
output reg[2:0]out1;
wire[2:0]net1;
always@(posedge clk)
begin
out1<=in1&&net1;
end
endmodule

W123:Identifies signals and variables that are read but not set
 EXAMPLE-8
module example8(out,clk);
When constant value is wider
input clk; than the width of a constant ,it
output out; results in truncation of extra
always@(posedge clk) bits.This trun leads to truncation
begin of extra bits data loss and
out<=1’b101; unexpected behaviour.
if(out==2’b101)
begin
-------
end
end
endmodule

W19:Reports truncation of extra bits

 EXAMPLE-9
module example9(clk,rst,d,q);
When a blocking assignment is used
input clk,d,rst;
in sequential block inherent
output q;
always@(posedge clk or negedge rst)
sequence of operation is implited in
begin simulation .However the
if(!rst) synthesisized hardware may behave
begin in aconcurrent fashion .Therefore
q<=1’b0; there is no assurance that gate
else levelsimulations match RTL level
Q=1’b1; simulations
end
end
endmodule

W336:Blocking assignments should not be used in a sequential block

 EXAMPLE-10
case1:
• Synthesis require that same variable or
out1<=in1&in2;
out2=in3&in4;
signal should not be assigned in blocking
case2: mode and non-blocking mode.
out1<=in1&in2; • Therefore there is no assurance that gate
out2<=in3&in4; level simulations match RTL level
case3: simulations.
out1=in1&in2;
out2<=in3&in4;
case4:
reg[3:0]reg a;
reg a<=1’b1;
reg a =1’b0;

W414:Reports non-blocking assignment in combinational block

 EXAMPLE-11
always@(en or d) In this example En is 0 so,the user not
begin mentioned /assigned the q value.
if(en)
q<=d;
end

W18:Do not infer latches

 EXAMPLE-12
fulladd u1(.in1(a[2:0]+b[2:0]); • Connection of a bus which is wider
.in2() than the port: excess bits are
---------- ignored for the input port and
); floated for output port.
• Connection of a bus which is
narrower than port: missing bits
are driven to unknown on input
ports and ignored for output port

W110:Identifies a module instance port connection that has in

compatible width as compared to port defination
 EXAMPLE-13
module example139(in1,in2,z);
Objects with real values have no physical
input in1,in2; equivalent and therefore not
output z; synthesizable by some synthesis tool.
real r=0.025;
assign z=r+in1+in2;
Real variables should be used only in test
endmodule
benches and simulation models.

W294:Reports real variables which are unsynthesizable.

 EXAMPLE -14
module example14(clk,in1,in2,out1);
input[1:0] in1,in2;
input clk;
output[1:0] out1;
reg[1:0] out1;
wire[1:0] count;
aasign count=(in1===1’b1):2’b10:2’b01;
always@(posedge clk)
begin
out1=(in2!==count)?in1:in2;
end
endmodule

W339a:Case equal to operator(===) and case not equal to operator(!==) may

not be synthesizable.
 EXAMPLE-15

module example15(in1,clk,out1,out2);
input in1,clk;
output reg out1,out2;
intial begin
out1=1’b0;
out2=1’b0;
end
endmodule

W430:The initial statement is not synthesizable

 EXAMPLE-16
module example17(in1,in2,out1); Signals missing from the sensitivity list can
input in1,in2; lead to a mismatch b/w pre and post
output reg out1; synthesis simulations.
always@(in1) The simulation only evaluates the changes in
begin combo logic when the signal in sensitivity
out1=in1&in2; change before synthesis.
end
endmodule
Synthesis process generates a logic which
reads all the required values wheather they
are present in sensitivity list or not.
Effectively the missing signals are added to
the sensitivity list and therefore ,post
synthesis simulation results are different
from pre synthesis simulation results.

W122:Reports a signal is read inside combinational always block but is not

included in the sensitivity list
 EXAMPLE-17
module example17(out1,in1);
output reg out1;
input in1;
always@(in1,out1) // right side variables can be in sensitivity list , not left side one
begin
out1<=in1;
end
Updating a signal from the
endmodule
sensitivity list inside the
always block may result in
erroneous simulation result.

W502:Ensure that variable in the sensitivity list is not modified inside

the always block
 EXAMPLE-18
If a signal is multiply assigned in
parallel conditional blocks and if those
always @ (clk)
conditions can be true simultaneously,
begin
the second assignment may override
if (clk)
the first. The rule reports such
begin assignments
out1<= in1; //Assignment of non-static value
if(en)
out1<= in2; // Violation It has a violation because it attempts
end to assign two different values to the
end same variable out1 within the same
clock cycle. This is known as a
multiple driver conflict.

W415a : Signal may be multiply assigned (beside initialization) in the

same scope
 EXAMPLE-19
If a signal is multiply assigned in
parallel conditional blocks and if those
always @ (clk)
conditions can be true simultaneously,
begin
the second assignment may override
if (clk)
the first. The rule reports such
begin assignments
out1<= in1; //Assignment of non-static value
if(en)
out1<= in2; // Violation It has a violation because it attempts
end to assign two different values to the
end same variable out1 within the same
clock cycle. This is known as a
multiple driver conflict.

W498 : Not all bits of a bus are read